资源列表
verilog-juanjima
- 卷积码是一种重要的前向纠错信道编码方式，其纠错性能常常优于分组码，且(2,1,7)卷积码已应用于现代卫星通信系统中。Viterbi译码算法能最大限度地发挥卷积码的优异性能。这里采用Verilog HDL语言设计出(2,1,7)卷积码的编码器模块和基于Viterbi算法的译码器模块，译码器采用全并行结构，译码速度快-Convolutional code is an important forward error correction channel coding method, and
USB
- 实现FPGA与PC通信的USB2.0接口,采用verilog语言实现-Implementation of FPGA and PC communication USB2.0 interface, using Verilog language to achieve
taximeter-in-verilog
- 本程序为出租车计价器的FPGA模拟功能实现，采用verilog语言编写。具体功能详见压缩包内的说明。-This procedure is for the taximeter FPGA simulation functions implemented using verilog language. You can see descr iption of the specific function in the rar package.
shuzijifenfa
- 基于EDA的数字积分法直线和圆弧插补算法的实现-Digital integration of EDA linear and circular interpolation algorithm
Beamforming
- 基于FPGA的波束形成，包括ad转换，数据存储等部分-FPGA-based beamforming, including ad conversion, data storage and other parts. .
CPLD
- 永磁同步电机伺服驱动器中使用的CPLD程序，主要配合DSP进行数据传输。-CPLD program which is used in servo conveter.
example_modbus
- 基于FPGA下的MODBUS通信驱动程序（RS-232通讯程序）-Based on MODBUS communication driver (RS232 communication program) FPGA under
YCbCr2RGB
- RGB 与YCbCr 颜色空间可以相互转化-RGB and YCbCr color space can be transformed into each other
PWM
- 基于FPGA的PWM控制器设计，包含ADC0820模块，按键扫描，PID，PWM控制器等模块，VHDL语言完成，已仿真通过-PWM controller design based on FPGA, including ADC0820 module, key scan, PID, PWM controllers and other modules, VHDL language completed, through simulation
Verilog-master
- 包含多个verilog源码，主要是AD7606的官方驱动，备注详细，学习参考。-Comprising a plurality of verilog source code, mainly AD7606 official driver, detailed notes, study reference.
Pmod_tr2
- FPGA pomd 接口演示实验包括蓝牙，gps，液晶显示等-FPGA pomd demonstration experiments interfaces including Bluetooth, gps, LCD, etc.
eda-class-v1.0
- 计算器功能，可加减乘除，可移位,65525以内运算-, calculator functions, addition, subtraction, multiplication, and division can shift, operation within 65525