资源列表
QPSK
- 这是用ISE编写的verilog语言的QPSK调制的代码-This is the QPSK modulation verilog language written with ISE code
AD9854(Altera)
- 这是个用FPGA编写的AD9854的驱动程序,它包含了FSK,PSK,ASK。-This is a written in FPGA driver of AD9854, it contains the FSK and PSK, ASK.
AX301_jtag_uart_test
- 黑金AX301开发板,jtag口驱动及调试实验代码-AX301 development board,JTAG port driver and debug experiment code
FPGA-Source-Code_VHDL
- cypress fx2lp slave fifo fpga控制端源码-source code of FX2LP_SLAVE_FIFO CONTROLLER S
LabVIEW超级玛丽
- 用LabVIEW编写超级玛丽游戏程序,可以哦学习、、
m-sequence_gen
- m序列生成verilog代码,经过仿真测试,绝对可用,带仿真说明-M sequence generated Verilog code, after the simulation test, absolutely available, with the simulation
msk_modulation
- 用verilog硬件描述语言写的msk调制程序,可以拿来参考一下-With verilog hardware descr iption language to write msk modulation process, you can refer
fsk_two1
- 基于verilog的2fsk解调的程序,调试通过,有需要可以下载来参考-The 2fsk demodulation based verilog program, debugging through, there is a need to download reference
MSK_top
- 基于verilog的MSK调制的程序,调试通过,有需要可以下载来参考 -Based on the MSK modulation verilog program, debugging through, there is a need to reference download
tlc549adc
- 利用状态机实现对TLC549的采样控制,实验时可调节电位器RW1(在开发板底板左下角),改变ADC 的模拟量输入值,数据采集读取后在数码管上显示。可以自己用万用表测一下输入电压, 然后与读取到的数据比较一下。注意:数码管显示的数据不是最终结果,还需要转换。 转换方法: 比如,采样电压值为V ,ADC转换后读取的8位二进制数为D,Vref为参考电压值,这里是2.5V 那么以下等式成立: V=(D/256)*Vref-Using the state machine to ac
Timing-
- 利用verilog设计的停车场中的计数器计时器和计费器,完成智能管理效果-Use the counter timer and meter parking lot in the Verilog design, intelligent management
dac_900
- DAC900芯片驱动的Verilog语言描述,亲测可用。另外的是FIR滤波代码和DDS波形发生器的代码。既可单独使用,也可以整合在一起。-DAC900 chips driven Verilog language descr iption, pro-test available. Another is the FIR filter code and DDS waveform generator code. Either used alone or can be integrated.