资源列表
rtl
- 液晶model 设计LCD 并口模式下的仿真model-LCD FIFO model
vhdl
- 慢码的vhdl，编码，解码，现在在做一个红外线的project.RC5 生成一个信号个给检测器，检测器会产生一组14 bits的数据流（是一组 曼彻斯特编码）。想用VHDL做一个解码器。-Slow code vhdl
DE2_PWM
- RC servo controller system using DE2
SFIFO
- 可以实现任意位的同步FIFO的verilog实现-the verilog code of a common SFIFO
rom16_1_16
- A basic 16 by 16 ROM memory
counter_net
- counter verilog code
display
- 八段数码管显示驱动程序，可用于多位显示的扩展-Eight out digital display driver can be used for the expansion of a number of display
FPGA_multiplier
- 本源码是用verilog语言编写的FPGA乘法器，可以输入两个8位数据，出输16位结果。-The source code is written in verilog FPGA multiplier, you can enter two 8-bit data, the output 16 results.
ADS1271
- VHDL的接口程序 24-bit 105ksps ADC 型号是：ADS1271 绝对稳定-VHDL interface program 24-bit 105ksps ADC models are: ADS1271 absolutely stable
aaa
- 24位加法计数器，每一个信号的上升沿将使得计数器加1，实现从0 -1 -2 -3…… -22 - 23的循环计数器。-24 States adding type counter， every rising-edge signal increases the counter, and making sequence 0-1-2-...-22-23 cycled.
QPSK_two1
- 基于verilog的QPSK解调的程序，调试通过，有需要可以下载来参考-Based on the QPSK demodulator verilog procedures, debugging through, there is a need to download reference
i2c_master_bfm
- i2c的master仿真模型,用于给slave发送cmd，data，等待slave反馈-i2c master behavial function model，for send cmd and data to slave, wait ack of slave