资源列表
sequence_detector
- verilog之序列检测，vivado工程，使用状态机的方式检测任意长度的数据顺序，提供四个检测工程，并全部带有Testbench,保证你能方便的学会序列检测这个知识点。-Data in a sequential manner to detect any length of sequence detection verilog, vivado engineering, using a state machine provides four detection project, and all w
PingPang_buffer_20160526
- 源码仿真 乒乓 缓存，实现数据流的传输，含有仿真测试文件，vivado工程。-Source simulation ping-pong cache data stream transmission, the file containing the simulation test, vivado project.
triplesdi
- Xilinx Triple SDI IP Sources
lms_adaptive_filter.vhd
- lms adaptive filter using desired and input stream to get the output with 4 tabs filter.
ddr
- ddr2控制器设计,适用于xilinx fpga,内含IP软核 -ddr2 controller design for xilinx fpga, embedded IP soft core
spi_rtl
- spi的rtl级代码设计，内含spi_slave和spi_master的行为模型-Rtl level behavioral model of spi code design, and includes spi_slave of spi_master
SDRAM
- 基于FPGA的nios ii嵌入式SDRAM应用开发程序，仅供参考学习使用，谢谢。-NIOS based on the II FPGA embedded SDRAM application development process, only reference learning to use, thank you.
musicplayer
- 基于FPGA的音乐播放器设计。能播放3首乐曲，播放过程可随时暂停或续播，可调C调与G调，音量可控制，可手动切换歌曲。-FPGA music player based on. Can play three songs during playback to pause or resume playback, adjustable C and G tune tone, volume can be controlled manually switch songs.
DE2-115_labs_verilog
- PDF格式的Verilog，DE2-115板的历程-PDF format Verilog, DE2-115 plate course
GTX4
- 光纤发送接收模块，verilog编写，主要用于光纤的发送和接收，波长1310nm-Fiber optic transmitter receiver module, verilog written primarily for transmitting and receiving the optical fiber, wavelength 1310nm
highspeed_96
- 高速数传QDPSK调制程序，V4板子可以用-High-speed data transmission QDPSK modulation process, V4 board can be used
09_SDRAM_VGA_Display_Test640480
- 在quartusII的开发环境下，编写的VerilogHDL语言的SDRAM通信程序，欢迎下载，这是基于Crazybingo的板卡环境设计-Under the development environment of quartusII, write SDRAM VerilogHDL language communication program, welcome to download, this is based on Crazybingo board environment design