资源列表
mys-xc7z020-lcd-xylon
- Zturn board verilog source with LCD driver.
LED_Display_Design_595Breathe
- LED呼吸灯，可更改LED灯位数，呼吸频率，等参数。(LED breathing lamp, can change the number of LED lights, respiratory rate, and other parameters.)
altera-de2-ann-master
- CNN implementation in Altera FPGA
-双路高速AD(AD9226)模块板发行资料
- 其中包括AD9226的原理图和应用程序，可以参考完成其他编程(Including AD9226 schematics and applications, you can refer to complete other programming)
VHDL2FSK
- VHDL 2FSK调制解调器各部分的原理与代码(The principle and code of each part of the VHDL 2FSK modem)
PWM
- 利用Verilog语言设计一个PWM控制器，实现：控制器输入时钟1MHz；控制器输出脉冲周期1kHz，脉宽最小调节步长0.1%。(The Verilog language is used to design a PWM controller, which is realized: the controller input clock 1MHz; the controller output pulse cycle 1kHz, and the pulse width minimum adjustme
vga_7_0728
- 用vga显示数字钟，通过串口可以控制时间显示(With vga digital clock, through the serial port can control the time display)
clock
- 自己开发的电子时钟小程序，通过数码管显示时间，key1和key2控制校时校分，key3切换时钟模式和闹钟模式，切换到闹钟模式再按key1和key2即可设定闹钟时间。key4控制开启/关闭闹钟。有整点报时功能。(Self developed electronic clock applet, through the digital tube display time, key1 and key2 control time correction, Key3 switch clock mode and
UART
- 自己写的uart实验程序，可通过按键选择波特率2400/4800/9600/19200，并通过数码管显示当前波特率。每按一次按键发送一帧数据，并通过两位数码管显示发送数据。可供新手学习。(The UART experiment program you write can select the baud rate 2400/4800/9600/19200 by key and display the current baud rate through the digital tube. Each
出租车计费器设计
- 实现出租车计费功能，可以在数码管上显示里程及费用(To realize taxi billing function, it can show mileage and cost)
Clock_Synchronization_Module
- 数字接收机中频部分数字时钟的设计 包括matlab仿真 verilog代码、 testbench代码 以及word设计文档(Design of medium frequency digital clock in digital receiver Including Matlab simulation Verilog, testbench code, and design documents)
FFT_Module
- 接收机数字部分FFT模块的代码 包括verilog代码、 matlab仿真、 word文档 testbench 实现FFT(The code of the digital part FFT module of the receiver Including Verilog, matlab simulation, testbench Implementation of FFT)