资源列表
qdq
- 基于ＦＰＧＡ的多路抢答器，采用Ｖｅｒｉｌｏｇ语言编写-FPGA-based multi-Responder, using Verilog language
sr12univ_a
- universal shift register vhdl
Spi
- 用于SPI接口通讯，用Verilog语言编写的SPI模块-SPI interface for communication with the Verilog language of the SPI module
connect_vhd
- 本程序的功能为检测输入信号范围是否在限定范围内，经ad转换器输入，经fpga芯片的Virtex4芯片输出来判断结果。-The functionality of the program for the detection of input signal range is within the limits, the ad converter input, the output fpga chip Virtex4 chip to determine the results.
CNT10
- 10进制计数器，使用altera芯片集成的80c51软核-10 binary counter, use the 80c51 chip altera soft-core
song
- 软件开发环境：ISE 7.1i 仿真环境：ModelSim SE 6.0 1. 梁祝乐曲演奏电路-Software development environment: ISE 7.1i simulation environment: ModelSim SE 6.0 1. Butterfly music concert circuit
code
- it is acode for shift register
view_quartus_simu_on_matlab
- 在进行Quartus仿真时，由于直接用自带的仿真工具无法查看正弦波，将仿真数据另存为tbl格式，用Matlab的程序调用该tbl文件，即可观察波形。当然，利用Modelsim更好。-During Quartus simulation, waveform directly with their own simulation tools can not view the sine wave, Save the simulation data for the tbl format, using the
MIPS_32numbers_32bits
- MIPS架构下的32位32个寄存器组的verilog源码-MIPS architecture 32 32 register banks verilog source
manchester_encoder
- 曼切斯特码解码器verilog程序，已通过ModelSIM仿真，可用-Chester Verilog decoder procedures, has been through the ModelSIM simulation, the available
counter_vhd
- An asynchronous (ripple) counter is a single d-type flip-flop, with its J (data) input fed its own inverted output. This circuit can store one bit, and hence can count zero to one before it overflows (starts over 0). This counter will increment once
ASKMod
- ASK调制信号的verilog VHL设计，在ise中实现了ASK信号的调制解调。-ASK modulation signal verilog VHL design, in ise to achieve the ASK signal modulation and demodulation.