资源列表
qdq
- 基于ＦＰＧＡ的多路抢答器，采用Ｖｅｒｉｌｏｇ语言编写-FPGA-based multi-Responder, using Verilog language
song
- 软件开发环境：ISE 7.1i 仿真环境：ModelSim SE 6.0 1. 梁祝乐曲演奏电路-Software development environment: ISE 7.1i simulation environment: ModelSim SE 6.0 1. Butterfly music concert circuit
code
- it is acode for shift register
view_quartus_simu_on_matlab
- 在进行Quartus仿真时，由于直接用自带的仿真工具无法查看正弦波，将仿真数据另存为tbl格式，用Matlab的程序调用该tbl文件，即可观察波形。当然，利用Modelsim更好。-During Quartus simulation, waveform directly with their own simulation tools can not view the sine wave, Save the simulation data for the tbl format, using the
MIPS_32numbers_32bits
- MIPS架构下的32位32个寄存器组的verilog源码-MIPS architecture 32 32 register banks verilog source
manchester_encoder
- 曼切斯特码解码器verilog程序，已通过ModelSIM仿真，可用-Chester Verilog decoder procedures, has been through the ModelSIM simulation, the available
counter_vhd
- An asynchronous (ripple) counter is a single d-type flip-flop, with its J (data) input fed its own inverted output. This circuit can store one bit, and hence can count zero to one before it overflows (starts over 0). This counter will increment once
ASKMod
- ASK调制信号的verilog VHL设计，在ise中实现了ASK信号的调制解调。-ASK modulation signal verilog VHL design, in ise to achieve the ASK signal modulation and demodulation.
speed_test
- QuartusII运行环境下的计数器的VHDL源代码，其中有部分文档说明。-QuartusII operating environment under the counter VHDL source code, some of them documented.
carLightsMealy
- carlights example with mealy based vhdl good for study
2s_Compl_2_4.0.vhd
- complement calculator
GAME
- 经典数学游戏 实现人猫狗鼠过河的经典游戏的状态机的编程-classic mathematic game