资源列表
user_logic_Open_I2C
- iic implementation,用verilog实现了IIC标准协议的功能-iic implementation, verilog achieved using standard protocols IIC function
ft_top
- 用quartus6原理编辑方式写的简易频率计我自己的实验来的 保证能使请您认真查看谢谢 -quartus6 principle used to write the editorial summary Cymometer my own experiments can guarantee you Thank you seriously View
XAPP678c
- xinlinx s vhdl code model and user guider-xinlinx's vhdl code model and the guiding user
cordic2
- cordic算法的vhdl实现，是用来实现极坐标同直角坐标之间变换。-cordic algorithm vhdl realized, is used to achieve a very Cartesian coordinates with the transformation between.
Verilog11
- 这个是用可编程器件进行仿真CPU的程序，大家一起分享拉-this device is programmable CPU simulation procedures to share with everyone Rafah
async_fifo1
- 要不要就看你了 要的话就下把 一切由你来顶 -should not depend on you to the next everything from the top of your to-huh
cpu86model
- 关于8086的软核fpga代码，可以直接再fpag的开发板上调试，好用而且是免费的-on the 8086 soft-core fpga code can then direct the development fpag board debugging, handy and free
987654
- 能够检测各种状态，能很好的实现功能，很有价值！-to detect a variety of conditions, and can achieve good functional and of great value!
shft_reg
- 用VHDL编的移位寄存器,具有置位,清零,装载,方向功能.~-VHDL addendum to the shift register is set, reset, loading, functional direction. ~
decdor_38
- 用VHDL编的编码器,具有多种功能,希望呢温暖感跟大家共享~!-VHDL addendum to the encoder, with a variety of functions and warm sense of hope do share with you ~!
licheng
- 本程序为Verilog扫描键盘成,然后送给51单片机处理的程序.-Verilog the procedures for scanning into the keyboard, then were sent to 51 micro-processing procedures.
taxi_counter
- 用VHDL编写的一个出租车计费器，起步6元计2公里，此后每半公里计0.8元，停车等待每2.5分计0.8元。通过仿真，但未下载到CPLD测试-a taxi prepared by the accounting device, starting six yuan or 2 km, then every half kilometer or 0.8 yuan, stopping to wait for every 2.5 minutes or 0.8 yuan. Through simulation,