资源列表
State.Machine
- State.Machine.Coding.Styles.for.Synthesis（状态机，英文,VHDL）-State.Machine.Coding.Styles.for.Synthesis (FSM, English, VHDL)
VHDL的基本数学运算库
- VHDL的基本数学运算库,非常好用-VHDL basic arithmetic library, a very handy! !
register reallocation
- 关于寄存器重命名register reallocation,VHDL-Register on rename register reallocation, VHDL
Silicon_Integrity，VHDL
- 信号完整性，设计FPGA的基础-signal integrity, design based FPGA
一篇用VHDL实现快速傅立叶变换的论文
- 一篇用VHDL实现快速傅立叶变换的论文，包括原理分析和代码实现，印度圣雄甘地大学M.A.学院提供-VHDL with a Fast Fourier Transform papers, including the principle of analysis and implementation of the code, the Mahatma Gandhi Institute of the University of Marat
VHDL实例
- 各种常用模块的VHDL描叙实例，PDF格式-various modules used VHDL depicts examples, PDF format
VHDL_交通灯系统
- 用VHDL语言编写，在MAXPLUS2下调试通过-VHDL language, debug through MAXPLUS2
fir.tar
- FIR滤波器的VHDL语言实现-The implement of FIR Filter based on VHDL
latch
- 门拴电路,4位选择器，alu,用verilog写的。-doors Shuan circuit, four selectors, ALU, with Verilog writes.
存储器模型及测试台
- 512x8存储器模型,及其测试台，用verilog写-512x8 memory model, and the tester, using Verilog write
16-bit数的偶数奇偶校验
- 16-bit数的偶数奇偶校验及阶乘运算，用verilog写-16-bit number of even parity and factorial computation, written using Verilog
微处理机接口电路设计
- 微处理机接口电路设计，用verilog写-microprocessor interface circuit design, writing Verilog