资源列表
HXRJTD
- 这是本人在Max plus2环境下用VHDL语言编的交通灯控制程序。做EDA课程设计的朋友可以下来参考参考。-This is my Max plus2 environment with VHDL addendum to the traffic lights control procedures. EDA design courses so friends from the reference reference.
DDS_SINWAVE
- matlab下，用dspbuilder实现dds模块产生正弦波的源码，-Matlab and used to achieve dds dspbuilder produce sine module source code,
PSKmoudel
- matlab下，使用dspbuilder实现的psk调制模块的源码-Matlab, the use of dspbuilder realized psk modulation source module
ASKmoudel
- matlab下，使用dspbuilder实现的ask调制模块的源码-Matlab, the use of dspbuilder realized ask modulation source module
comple_mult
- matlab下，使用dspbuilder实现的复数乘法器模块的源码-Matlab, the use of the plural dspbuilder achieve multiplier module FOSS
iictestbench
- vhdl写的完整i2c代码,有仿真文件,是清华的人写的,质量可靠,请大家交流,qq:398087764-vhdl the integrity i2c write code, simulation document, the writers of Qinghua, reliable quality, Please exchange qq : 398087764
fir_finall
- 用verilog编写的fir滤波器程序，开发环境可以用ise quartus或active hdl等-verilog prepared with the fir filter process development environment can be used ise quartus or other active hdl
uart-verilog-vhdl
- 拿verilog和vhdl编写的串口通信代码(可综合)-with vhdl and verilog prepared by the serial communication code (synthesis)
clk_div2n
- 这是用VHDL 语言编写的参数可以直接设置的2n倍时钟分频器，在运用时，不需要阅读VHDL源代码，只需要把clk_div2n.vhd加入当前工程便可以直接调用clk_div2n.bsf。-This is the VHDL language parameters can be directly installed 2n times the clock dividers, when exercising not reading VHDL source code, clk_div2n.vhd simp
COUNT_10
- VHDL源代码.设计一个带有异步清0功能的十进制计数器。计数器时钟clk上升沿有效，清零端为clrn,进位输出为co。 -VHDL source code. Asynchronous design with a 0-counter function of the metric system. Counter clock clk ascending effective end to reset clrn, rounding output co.
COUNT_4qiduan
- VHDL源代码.设计一个模为4的计数器，并在实验箱上用七段数码管显示结果-VHDL source code. Design a scale of four counters, and the experimental box used in paragraph 107 of Digital Display Results
renyizhengshufenpingdeVHDLdaima
- 本文件是实现任意整数分频的VHDL代码,愿与大家分享!-this document is arbitrary integer frequency VHDL code, and is willing to share with you!