资源列表
loadGIF
- 使用sdk读取GIF文件 需要相应的vgsdk库来运行项目-use sdk read GIF files need vgsdk corresponding to the operation of the project
clock_top2
- 数字钟的vhd文档，个人感觉还是蛮完善的，大家可以下载了一同改进。-figures minute vhd files, individuals still feel pretty good, we can improve downloaded together.
spant
- 一个在spantan3上实现的24路分频VHDL程序，实现方法简单，并且在硬件电路上跑过，可以直接使用。可以进一步修改成PWM程序。-a spantan3 achieved in the 24-way frequency VHDL procedures, simple, and the hardware circuits once ran can be used directly. Can be further modified as PWM procedures.
DCFQ
- 经典触发器，对初学者会非常有用的，希望可以多交流下。-classic triggers for beginners will be very useful and hope more exchanges under.
ASYfifo
- 这是FIFO程序，开发工具是ISE或QUartus。-procedures, development tools or QUartus ISE.
cdkz
- vhdl编写的彩灯控制程序，比较简单，仅供初学者参考-vhdl prepared by the Lantern control procedures are relatively simple, reference is for beginners
zlqdq
- vhdl编写的智力抢答器程序，比较简单，仅供参考-vhdl prepared by the intelligence Responder procedure is relatively simple, for information purposes only
led_decode
- 用veilog HDL编的七段译码显示电路。自己做的第一个此类程序，编译仿真通过，感觉不错-veilog HDL series with paragraph 107 of the decoder show circuit. I have done the first such procedure, compile through simulation, feeling good
count_usebasketball
- 一个小程序，用Veilog HDL编写的，可以用于篮球比赛的倒计时牌，已在max-plusII上仿真通过。-a small program, prepared by the Veilog HDL, can be used for the basketball game countdown. have max-plusII on through simulation.
risc_spm
- advanced digital design with the verilog hdl-advanced digital design with the verilog h dl
CSpeed
- 采集电压 用研华6220板卡采集电压值 实时显示 电压变化-Acquisition voltage with Advantech 6220 Card Collecting real-time display voltage voltage changes
byvhdstopwatchl
- 1.高精度数字秒表（0.01秒的vhdl语言实现） 2.具有定时，暂停，按键随机存储，翻页回放功能； 3.对30M时钟分频产生显示扫描时钟 4.精度高达0.01s,并且可以通过改变主频来更改分频比和记数间隔，可控性高。 5.模块化设计，其中的许多函数可以成为vhdl语言的通用经典例子（包含分频电路设计，动态扫描时钟设计，译码电路设计，存储器设计，存储回放显示设计）-1. High-precision digital stopwatch (0.01 seconds vhdl la