资源列表
fpga_spi
- 文件中包含有用fpga实现isp接口的源码,以及和处理器接口,测试时处理器是ARM7。-document contains useful fpga achieve isp Interface source, as well as the processor interface, testing is ARM7 processor.
FPGA_SONGER
- 基于FPGA的乐曲硬件演奏电路设计的实现,有完整的VHDL代码,并有PDF详细说明如何下载及跳线设置,并“梁祝”在GW48系列开发平台上下载调试成功。音乐优美-FPGA-based hardware music concert circuit design to achieve a complete VHDL code. and a detailed account of how the PDF download and set up the jumper, and "Butterfl
FPGA_TENNIS
- 基于FPGA的乒乓球游戏硬件电路的设计与实现,有完整的VHDL代码,并有PDF详细说明如何下载及跳线设置,并在GW48系列开发平台上下载调试成功-FPGA-based table tennis game hardware circuit design and realization of a complete VHDL code. and a detailed account of how the PDF download and jumper settings and in a series
VHDL-ysw
- 基于CPLD的棋类比赛计时时钟,第一个CNT60实现秒钟计时功能,第二个CNT60实现分钟的计时功能,CTT3完成两小时的计时功能。秒钟计时模块的进位端和开关K1相与提供分钟的计时模块使能,当秒种计时模块计时到59时向分种计时模块进位,同时自己清零。同理分种计时模块到59时向CTT3小时计时模块进位,到1小时59分59秒时,全部清零。同时,开关K1可以在两小时内暂停秒钟计时模块,分钟计时模块和小时计时模块。各模块的VHDL语言描述如下:-CPLD-based time clock chess c
CUS_SPI-VHDL
- 此为VHDL的SPI通信代码,全部在一个压缩包中,请仔细阅读后再使用.-this as VHDL code SPI communication, all in a compressed package, please read carefully before use.
samll
- 这是一组Verilog的代码小程序,适合新手练习使用.-This is a group of small Verilog code procedures for the use of novice practitioners.
firISPdesign
- fir ISP design fir VHDL VHDL编程滤波的硬件描述语言实现,包括VHDL语言和verilog语言-fir fir VHDL design ISP programming VHDL hardware descr iption of the filter language , including the VHDL language and verilog
IP_SPI
- spi总线的vhdl代码,试了试可以用。希望能对开发者有所帮助。-spi bus vhdl code Shileshi can use. The hope is to help developers.
Verilog_FPGA_fp
- 用Verilog实现基于FPGA的通用分频器-using Verilog FPGA-based Universal Frequency Divider
verilog_latch
- verilog实现锁存器,共有四个文件,包含测试文件-verilog achieve latches, a total of four documents, including test paper
verilogfifo
- verilog HDL实现先进先出栈,不含测试文件-verilog HDL achieve first-in first-out stack, non-test document
VHDLDPLL
- 比较好的技术文章《基于VHDL的全数字锁相环的设计》有关键部分的源代码。-relatively good technical article, "based on VHDL DPLL the design" a key part of the source code.