资源列表
VHDL_TIMESET
- 本专题之研究，为使用硬件描述语言VHDL规划成自己所需要的硬件控制电路，配合上FPGA可程序化硬件设备中的相关模组，而发展出一套数位电子钟之控制器实现。-study of the topic, for the use of VHDL hardware descr iption language into their planning the necessary hardware control circuit, coupled with FPGA hardware program to the
PUKverilogPPT1-9PAGE
- 我收藏的北京大学的verilog的PPT,希望对大家有用,这是1-9章,随后上传剩下的-collection of the Beijing University verilog the PPT, a member of the useful, which is 1-9 chapter Subsequently the remaining Upload
add_16_pipe
- 16位加法器的流水线计算,verilog代码，用于FPGA平台。-16 pipelined adder, verilog code for the FPGA platform.
Viterbi_v
- Viterbi算法的Verilog源代码。-Viterbi Algorithm Verilog source code.
FIR_vhdl
- 基本FIR滤波器的VHDL源代码及其测试程序。-basic FIR filter VHDL source code and testing procedures.
SPI_Core.ZIP
- SPI协议的VHDL/Verilog语言实现。-SPI agreement VHDL / Verilog language.
DSP_FPGA_vhdl
- 数字信号处理的FPGA实现(第二版）书的源代码。-digital signal processing on FPGA (2nd edition) the source code.
ledleft
- xilinx的SPARTAN-3E入门开发板实例 根据官方公布的led移动范例改写。 原范例仅提供了源代码、烧写文件以及dos窗口下使用的烧写bat文件。 本实例采用了ise7.1i创建，在ise下重建整个工程，有助于初学者理解使用。-xilinx the SPARTAN-3E portal development board examples According to the official announcement led to the mobile Examples rewr
feizhenshu
- 非整数分频器 分频系数为无限不循环小数 vhdl-non-integer frequency divider coefficient of circulator is not unlimited vhdl
AsynCommCtrl
- 基于VHDL的串行异步通信电路的设计 包括串行发送器，异步接收器，以及控制器 vhdl-VHDL-based serial asynchronous communication circuit design, including serial transmitter, asynchronous receiver. and controller vhdl
xiyiji
- 洗衣机控制器，包括清洗、漂水、脱水等状态，vhdl-washing machine controller, including cleaning, bleaching water, dehydration state, vhdl
i2c_7111_7128
- vhdl,用i2c控制philips的7111和7128-vhdl, and the i2c control philips 7111 and 7128