资源列表
I60BCD
- I60BCD是一个数字钟的显示模块，你也可以把它改装成别的器械显示用-I60BCD is a digital clock display module, you can also modified it into other equipment Display
duogongnengdianzizhong
- 具有整点报时功能,整点时响铃5s。具有控制启动和关闭功能。 具有调整起床铃,熄灯铃时间的功能。 具有调整打铃时间长短和间歇时间长短的功能。 -with whole point timekeeping function, the whole point ringing 5s. Have control startup and shutdown functions. Get up with adjustments bell, lights-out bell time function.
vgactrl
- vga控制电路原码。主要有时序产生模块，彩条产生模块和接口模块。改程序主要用状态机来实现，两个计数器来控制状态的翻转。-vga control circuit original code. Sequencers have a major modules of exotic produce modules and interface modules. Procedures in the main state machine to achieve, two counter to the state
xapp935
- ddr2 controller, verilog source code from xilinx
656to601
- 本程序实现视频图象的CCIR656转换CCIR601格式,使用的环境是Quartus II 4.0-the program CCIR656 video image conversion CCIR601 format, The environment is the use of Quartus II 4.0
isatoi2c
- 本程序实现的是ISA转I2C的功能,绝对可用-this program is the ISA I2C transfer function can be absolute
VerilogHDLchinapub
- Verilog HDL硬件描述语言 01简介.PDF 02HDL指南.PDF 03语言要素.PDF 04表达式.PDF 05门电平模型化.PDF 06用户定义原语.PDF 07数据流模型化.PDF 08行为建模.PDF 09结构建模.PDF 10其它论题.PDF 11验证.PDF 12建模实例.PDF 13语法参考.PDF-Verilog HDL Hardware Descr iption Language Introduction 01. P
chip1
- CPLD的程序,分频,微分等,应用于DPLL -CPLD procedures, frequency, differential, etc. can be applied to DPLL
S1_38yima
- 1、本程序模仿3/8译码器的功能 2、由拨码开关输入，led输出。-1, the procedures imitate 3 / 8 decoder function 2, code switching from the allocation of import, export led.
dds-design
- DDS design with vhdl language.
TFT_LCD_IP
- TFT_LCD控制电路CPLD_IP设计-certified CPLD_IP control circuit design
Open_Verilog_International_-_VERILOG-HDL_PLI_Refer
- pli的文档资料，是cadence出的，详细介绍了pli的使用方法-pli document, the cadence is introduced in detail the use pli