资源列表
4_10_vhdl
- 这是老师给但计数器程序，经过自己刚才调试过了，真的成功了，哈哈……，有需要就看看吧-This the teacher but to counter procedures, testing himself just over a really successful, ha ha ... there is a need to watch it!
VerilogHDLjihe
- 王金明的Verilog HDL程序集合，包含各个常用的程序-guo Verilog HDL procedures set includes all commonly used procedures
I2C_loader
- 用FPGA做主控制器，对IIC从设备配置参数的源程序。Xilinx提供-FPGA master controller, right from the IIC equipment configuration parameters of the source. Xilinx offer
422_to_444
- YUV422转YUV444的FPGA插植算法，由Xilinx提供-YUV422 to YUV444 FPGA implantation algorithm provided by Xilinx
ycrcb_rgb
- YUV转RGB的源程序，使用到了硬件加速器，可利用FGPA的乘法器加速处理速度。-YUV to RGB source, the use of a hardware accelerator, FGPA can be used to speed up the processing speed multiplier.
deinterlace
- Xilinx提供的一种利用线缓存进行插值的隔行变逐行程序，比普通算法效果有很大改进。-Xilinx to provide a linear interpolation for the cache interlaced progressive change procedures, than ordinary algorithm results are greatly improved.
ModelSim_TestBench_VHDL
- ModelSim TestBench的VHDL模版-ModelSim VHDL template TestBench
N_counter_VHDL
- 任意N进制分频器的标准VHDL代码（原创）-arbitrary N divider 229 standard VHDL code (original)
PulseWidth_detector_VHDL
- 通信控制中常用的脉冲宽度检测程序，VHDL模块化编成实现（原创）-communication control used in pulse width detection procedures, VHDL modular organization to achieve (original)
even_divider_VHDL
- 常用2、4、6及任意偶数分频器的VHDL代码实现（原创）-used 2,4,6 and even arbitrary divider VHDL code to achieve (original)
odd_divider_VHDL
- 常用1、3、5及任意奇数分频器的VHDL代码实现（原创）-used 1,3,5 and arbitrary odd Divider VHDL code to achieve (original)
Synthesisofverilog
- 一篇有用的Verilog语言综合问题研究-a useful comprehensive Verilog language study