资源列表
openmsp430_latest.tar
- 开源的MSP430 Verilog源码，供学习使用-Open Source MSP430 Core verilog code, for studying.
ad9854_z1_first
- ad9854的xilinx代码，verilog代码，调试通过的-ad9854 xilinx code, Verilog code, debugging through
kt1
- 基于FPGA的可控100进制可逆计数器，运行环境maxplus-Controlled 100 hex reversible counter FPGA-based operating environment maxplus
miniprinter
- 微型打印机模块实验.rar；基于FPGA-2C35核心；博创实验箱平台。 在quartusII里面添加uart核，nios II的Console构成人机交互界面，串口与微型打印机通信，打印出数据。 -Micro printer module experiment rar core on the FPGA-2C35 Borch experimental box platform. QuartusII inside to add the uart nuclear, nios II Con
an-8-bit-left-shift-register
- 使用VHDL语言设计一个8 位左移移位寄存器。并给出了仿真波形。-Using VHDL to design an 8-bit left shift register. And simulation waveforms.
eetop.cn_tcd1209
- TCD1209D 时序驱动采用VHDL语言-TCD1209 drive
ds18b20_seg7
- 基于 FPGA+ds18b20 温度计 设计 一ds18b20接受 数据 以数码管 显示温度-Designed based on FPGA+ Ds18b20 thermometer ds18b20 accept the data to the digital display temperature
QPSK_fpga
- QPSK调制和解调的FPGA实现，包括伪码生成等模块-QPSK modulation and demodulation of the FPGA, including the pseudo-code generation modules
EDAshipinchuli
- 采用FPGA芯片对，CCD摄像头的输出的模拟视频信号进行采集，转换为640*480分辨率的视频数据，并暂存于外部SRAM或SDRAM中-The FPGA chip, the output of the CCD camera analog video signal acquisition, converted to 640* 480 resolution video data, and temporarily stored in the external SRAM or SDRAM
scramble
- 在quartusII上已经验证过，很有用的并行加扰程序，用的语言为verilog，需要的可以拿去-Has already been verified in quartusII useful parallel scrambling procedure, the language used for Verilog, need to take look at
i2c
- i2c配置adv7180 将模拟信号转成数字信号bt656-i2c configuration adv7180
32-crc32
- 32位数据输入并行算法Verilog HDL代码。-32 bits of data input and parallel algorithm Verilog HDL code