资源列表
TLC_5620_sin
- 利用TLC5620产生正弦波，频率47HZ，幅值2.08-Use TLC5620 produce sine wave
encoding-decoding
- 卷积码编码译码程序以及其modelsim仿真波形文件等-Convolutional code encoding and decoding procedures and the Modelsim simulation waveform file
OneD_DCT8
- 一维DCT变换，使用Verilog ＨＤＬ语言实现。有ＳＹｎｐｌｉｆｙ编译脚本-One-dimensional DCT, using the Verilog HDL language to achieve. The SYnplify compiled scr ipt
CPLD-Three-voting
- CPLD/FPGA 设计实例手册 用VHDL语言设计三人表决器 用原理图输入的方式设计三人表决器 用verilog-HDL语言设计三人表决器-CPLD/FPGA design example manual Three of the voting machine VHDL language Schematic design of a three-member voting Verilog-HDL language design three-member voti
v-watch
- 基于fpga的数字电压表的设计，包括ad转换，bcd码转换，分频，3选1模块，小数点生成模块，显示模块组成。-Based on the FPGA digital voltage meter design, including AD conversion, BCD code conversion, frequency,3 choose1module, a decimal point generating module, display module.
Electronic-Lock-(VHDL)
- 开锁代码为2位十进制并行码。 当输入的密码与锁内的密码一致时，绿灯亮，开锁；当输入的密码与所内的密码不一致时，红灯亮，不能开锁。 密码可由用户自行设置。 密码可由七段数码管显示出来。 -The design is based on the VHDL language, using the MAX+ plusII parallel electron two locks design, and design process described in detail. VHDL lan
verilog-state-machine
- 使用VerilogHDL语言的小教程。 用三段式方法编写状态机。 有清晰详细的注释。-A small tutorial teaching how to write the state machine using three-step method in VerilogHDL language. There are clear and detailed notes in the tutorial.
Perfect-VHDL
- 1 步进电机定位控制系统VHDL程序与仿真 2 采用等精度测频原理的频率计程序与仿真 3 URAT VHDL程序与仿真 4 自动售货机VHDL程序与仿真 5 电子琴程序设计与仿真 6 出租车计价器VHDL程序与仿真 7 DAC0832 接口电路程序 8 FSK调制与解调VHDL程序及仿真 -1stepper motor positioning control system for VHDL procedures and simulation
fft256
- 利用quartusII提供的FFT IPcore设计的256位的FFT，并附有testbench文件-Provided by quartusII the FFT IPcore design 256 FFT with testbench file
s101
- 用VHDL语言，设计一个“101”序列检测器，双过程描述编写-VHDL language, to design a dual procedure describes the preparation of "101" sequence detector.
ADC_Ctrl
- 用verilog编写FPGA与AKM394A之间的接口程序-Verilog between FPGA and Ak5394A interface code
ad_converter
- 基于spi接口的数模转换控制（FPGA verilog源码）-Spi interface-based digital-analog conversion control (FPGA Verilog source code)