资源列表
84f704a6df6c
- 介绍数字锁相环的基本结构,详细分析基于FPGA的数字锁相环的鉴相器、环路滤波器、压控振荡器各部分的实现方法,并给出整个数字锁相环的实现原理图。仿真结果表明,分析合理,设计正确。-MC145159 PLL frequency synthesizer design and realization of PLL frequency synthesizer the basic principles of integrated PLL chip M C 145159 work characteristic
IR
- 来自著名公司半导体公司IR的基于FPGA的AC伺服电机设计-FPGA based AC Servomotor-Control Designs from IR
Rake_Receiver
- 用Verilog HDL语言实现一个Rake接收机的最大比合并准则，其中3路输入数据是并行相关输出-Verilog HDL language with a Rake receiver maximum ratio combining criteria, of which 3 related to the parallel input data is output
Verilog_FPGA_DDS
- Verilog编写基于FPGA的DDS实现-FPGA-based DDS Verilog
fa0fdm
- 这是很有用的VHDL和VERILOG 的源代码，我是买过的来的，觉得太有用了，特此共享，对于学习OFDM的人来说，是太难得了！-This is useful VHDL and VERILOG source code, I bought in the past, I feel so useful, and hereby share, for the people who study and OFDM, is too hard won!
clock
- vhdl 数字钟工程文件夹 解压就可以用 quartus ii工程文件 -vhdl digital clock project folder can be used to extract the project file quartus ii
sramceshi
- 用VERILOG编写的测试SRAM代码，已通过板级测试，完整无误-SRAM with the VERILOG code written test, have passed the board-level test, complete and correct
xapp921c
- Xilinx的ddc duc的文档 xapp921c-xapp921c
ADCTR
- 基于VHDL实现AD7891转换时序的控制器-perfect progranm by vhdl
recovery
- 恢复时钟信号的代码,用于数字通信中，used to recovery the timing from data-used to recovery the timing from data
Adder_Kogge_Stone_32bit_With_Test_Bench
- verilog source code and test bench of Adder Kogge Stone 32-Bit
7_1LVDS_serilizer
- 7:1LVDS编码 为LVDS方面需求的人提供参考设计，很高兴- This VHDL or Verilog source code is intended as a design reference which illustrates how these types of functions can be implemented. It is the user s responsibility to verify their design for consistency a