资源列表
UART
- UART发送verilog源码，波特率115200，以及testbench源码-Send verilog source UART baud rate 115200, and testbench source
DS18B20ss
- 使用fpga硬件语言写的DS18B20程序，altera的fpga，单总线测试可用-altera fpga ds18b20
cop2000
- 模型机仿真的VHDL语言描述，在xilink9.1环境中实现。-VHDL simulation model of machine language to describe, in xilink9.1 environment implementation.
D_chufa
- 在QuartusII软件环境下，编写的移位寄存器的实现，包含仿真波形；-Quartusii software in the circumstances of the shift register, containing simulation waveforms
SAR-Signal-Simulation-of-FPGA-based-fast-way
- 基于FPGA的SAR回波仿真快速实现方法SAR Signal Simulation of FPGA-based fast way-SAR Signal Simulation of FPGA-based fast way
DNC12-test
- 128细分的步进电机驱动程序，有需要的朋友可以看看。-128 segments of the stepper motor driver, a friend in need can look at.
Virtex2_Manual
- Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, downlo
dll
- 在传输数字信号的时候，需要时钟定时，本程序可以从数据中恢复出时钟-In the transmission of digital signals, the need for clock timing, the program can recover a clock from the data
yt7132_clock
- 用VHDL语言编写的12/24小时时钟，利用EDA系统软件QuartusII环境下基于FPGA/CPLD的数字系统设计方法-VHDL language with the 12/24 hour clock, the use of EDA software QuartusII environment based on FPGA/CPLD design of digital system
3_3_mean_diltter(ALU)
- 3*3均值滤波的VHDL语言实现的工程，对红外图像进行有效的去噪处理。这是其中的ALU模块，专门用来测试其延迟状况的模块。-3* 3 mean filter VHDL language works effectively on the infrared image denoising. This is one of the ALU module, designed to test the status of the module delay.
chuzuche
- FPGA出租车的制作最终程序,实现自动计价功能。-The production of the final program FPGA taxi, automatic pricing feature.
gradtobin
- 格雷码转二进制的程序（verilog），经过验证quartus、8.1-grad to binary