资源列表
Walsh
- 利用ISE编写的产生WALSH码的verilog程序，简单易懂，稍稍修改就可以产生出自己想的8 16 32 64位的WALSH码-Prepared using ISE verilog code generated WALSH procedures, easy to understand, a little modification can generate their own like the 8,16，32，64-bit code WALSH. .
VHDL语言写的简易计算器
- 用VHDL写的简易计算器，包括加减乘除，除法器用加法器和乘法器组成-Write simple calculator with VHDL, division, including add, subtract, multiply and divide adder on time-multiplier and used
iscas89_verilog
- Verilog HDL 时序基准电路 ISCAS89-ISCAS89 sequential benchmark circuits Verilog HDL
jtag
- verilog jtag源码及原理，还有debug模块。边界扫描等-verilog jtag source and principle, as well as debug module. Boundary-Scan, etc.
pal_vedio
- 基于FPGA的pal制模拟视频显示程序，verilog Hdl-pal-d vedio display fpga verilog
ad_test
- ad9777的测试程序，对SPI进行初始化，运用ISE环境，成功地进行综合和实现-ad9777 test procedures, the SPI is initialized, the use of ISE environment, the successful realization of comprehensive and
spi_controller
- SPI控制器，基于VERILOG描述，分模块设计，共6个模块，时钟产生模块，移位模块，主模块，从模块，定义模块，顶层模块。-SPI controller, based on the VERILOG descr iption, sub-module design, a total of six modules, clock generation module, shift module, main module, from the modules, custom module, top modul
xlx_s6_lx150t_dev-sch-revc032510
- avnet Spartan-6开发板原理图-avnet Spartan-6 development board schematics
FPGA-VIDEO
- FPGA图像采集程序，cmos图像采集、I2C控制、VGA图像像是模块-FPGA VIDEO
Chapter6-9
- 第六章到第九章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例
fir_lms
- 基于FPGA的自适应滤波器的实现。采用Verilog编程，2阶滤波器。-FPGA-based realization of the adaptive filter. Using Verilog programming, 2-order filter.
UART
- 使用Quartus ii软件，编程语言为Verilog语言，实现UART通信协议，FPGA的时钟信号为50MHz-Using the Quartus ii software, programming languages Verilog, UART communication protocol implementation, FPGA 50MHz clock signal