资源列表
WM_8776
- WM8776控制模块，直接调用为24位、44.1KHZ采样和输出，开启耳机输出。如需更改可将DA，AD和控制模块分别独立-WM8776 control module, a direct call for the 24-bit, 44.1KHZ sampling and output, open the headphone output. For a change can be DA, AD and control modules separately
50604
- vhal语言数字时钟设计 fpga cpld -vhdl
videodigitalsignalscontroller
- 使用Verilog语言编写的SRAM源码，可以移植，方便51控制-failed to translate
test_bech
- verilog + testbench 文件的读写操作-verilog+ testbench
count100
- 用VHDL语言编写的100进制计数器，计数到99后清零-VHDL language with the binary counter 100, count to 99 after the clear
SinglePeriodCPU
- verilog语言书写，单周期CPU源码-single period CPU
plc
- QSPLC系列可编程控制器实验 数码显示的模拟控制 交通灯的模拟控制（控制过程、I/O分配、控制语句表、梯形图）-QSPLC series programmable controller experimental digital display analog analog control traffic light control (control process, I/O distribution, control statement table, ladder)
bcd
- 4位bcd码加法器的verilog代码 -4 bit bcdadder verilog4 bit bcdadder verilog
DSB3
- 利用ISE软件编写的Verilog程序，可以进行信号的双边带调制-Using ISE software program written in Verilog, can be bilateral with a modulation signal
cordic
- altera cordic ip core, 包含文档，完整设计，以及测试向量-altera coedic ip core, including the document, whole design, and the testbench.
xiangweileijiaqi
- 相位累加器，是数字频率合成器的重要组成部分。这是verilog代码。-Phase accumulator, digital frequency synthesizer is an important part. This is the verilog code.
I2C
- I2C总线接口的Verilog源码文件和modelsimd的测试文件-Verilog source code of I2C bus interface and testbench code of modelsim.