资源列表
CPU11111
- altera提供的sdram ip核例程，简单易懂。采用burst8模式。 -altera provided by the sdram ip core routines, easy to understand. Using burst8 model.
viterbi
- verilog code for viterbi encoder and decoder
AUTO_START
- verilog 编写的代码 方便使用 能自启动的七进制计数器-verilog code written in easy to use can be self-starting of the seven binary counter
3424312413414
- 基于FPGA的CMI编码器和译码器的实现源代码-the cmi decoder and encoder based on FPGA
PWM
- 用VERILOG语言编写的PWM驱动电机的实验,可控制绝大部分实验箱上的步进电机-PWM DRIVER
icmp
- VHDL implementation of ICMP protocol tested
VHDL_LCD1602
- 用FPGA来实现液晶LCD1602的读写显示操作的程序代码。-Using FPGA to implement reading and writing LCD1602 LCD display operation code.
eda
- 利用FPGA可编程芯片及Verilog HDL语言实现了对直流电机PwM控制器的设计，对直流电机速度进行控制。介绍了用Verilog HDL语言编程实现直流电机PwM控制器的PwM产生模块、串口通信模块、转向调节模块等功能，该系统无须外接D／A转换器及模拟比较器，结构简单，控制精度高，有广泛的应用前景。同时，控制系统中引入上位机控制功能，可方便对电机进行远程控制。-Using FPGA programmable chip and Verilog HDL language for the desi
sc_camera_01APR08
- 基于FPGA的CMOS 传感器的图像传输处理.整个设计还基于NIOS.-FPGA-based CMOS sensor Image Transmission. The design is also based on NIOS.
E8051_256
- This contains the main-level VHDL files required for an example complete, ready-to-use, FPGA/ASIC 8051 microcontroller. The corresponding main schematic can be found in the Schematics folder, and a technical descr iption of the e8051 core inter
jiafaqi
- 用Veriloge编的四位二进制加法器。用一个显示屏进行显示。-Veriloge series with four binary adder. With a display to display.
sram_512x16bit
- SRAM的控制器，与sopc集成，可直接使用，方便稳定高速，简单修改可适应于其他容量-SRAM Controller in SOPC