资源列表
TIMEFACEDETECTIONANDLIPFEATUREEXTRACTIONUSINGFPGA
- Abstract—This paper proposes a new technique for face detection and lip feature extraction. A real-time field-programmable gate array (FPGA) implementation of the two proposed techniques is also presented. Face detection is based on a naive Bay
Xilinx-FIR
- 基于Xilinx FPGA实现的系数可装载数字滤波器源代码-Configurable Digital Filter Based on FPGA (using Verilog under Matlab 2008a)
Advanced_Digital_Design_with_the_Verilog
- Verilog 语言的高级数字系统设计，原版书籍，很全面-Verilog language, advanced digital system design, original books, very comprehensive
sdram_controler
- SDRAM 读写控制器的 verilog 三星公司源代码-verilog design for SDRAM read and write
fir
- 数字电路设计中的，fir滤波器设计，我做的是8位宽的，利用vhdl实现，附带了完整的代码，报告，我没有对我的信息进行删除，是希望大家能够诚实的利用这个代码，提高自身本领。-Digital circuit design, fir filter design, I am doing is 8 bits wide, using vhdl implementation, with a complete code, the report, I did not delete my information i
altera_up_avalon_irda
- Altera大学计划的红外通讯IP，avalon接口-Altera University Program of the infrared communication IP, avalon interface
32bitBoothmultiplier
- 32位布思乘法器VHDL实现，2个32位数相乘-32-bit Booth multiplier VHDL implementation, two 32-digit multiplication
clock1
- 多功能数字钟实现闹铃，整点报时，校时，仿广播电台报时功能-multifuntional digital clock written in verilog
i2c_master_model
- i2c仿真model,可用于整体的FPGA仿真系统,用于i2c slave 设计的正确验证-i2c simulation model, the FPGA can be used for the whole simulation system designed for the proper verification i2c slave
I2C_slaver
- I2C从端，用于接收master的控制信号 verilog-I2C from the side, for receiving master control signal verilog
SEED-FEM025
- 合纵达FPGA开发板，原理图V-4系列，包括powerpc-fpga
fir_dec3
- FIR抽取滤波器，抽取系数3，Verilog版本，数字下变频-FIR decimation filter, extraction coefficient of 3, Verilog version of the digital down-conversion