资源列表
DigitalClockVHDL
- 多功能电子时钟的VHDL源代码。使用MAX+PLUS II进行编译。该文档有详细的说明和程序注释。-VHDL source code. Use MAX PLUS II computer. The document is described in detail in the Notes and procedures.
simple_cpu
- 初学cpu结构的很好的verilog代码的示例，适合初学者-novice cpu structure of the good verilog code examples for beginners
sdram_verilog
- 这是使用VERILOG语言，基于MICRON公司的SDRAM开发的SDRAM接口逻辑-verilog This is the use of language, MICRON-based company's development of the SDRAM SDRAM interface logic
traffic2
- 用verilog编的小程序,希望对需要的人有所帮助-verilog series with a small procedure, and I hope to the people in need some help
verilogled
- cpld-epm7128stc100-10驱动四位LED结果显示1234-cpld - epm7128stc100-10 drive four LED 1234 results
cpldPWM
- verilog HDL 编写的PWM，是初学CPLD者入门Z资源，epm7128stc100-10-verilog HDL prepared by the PWM, is a novice CPLD Getting Started Z resources, epm7128stc100-10
mouse_control
- 1、 用FPGA实现PS/2鼠标接口。 2、 鼠标左键按下时十字形鼠标图象的中间方块改变颜色，右按下时箭头改变颜色。 3、 Reset按键：总复位。 -one with FPGA PS / 2 mouse interface. 2, the left mouse button pressed cruciform images in the middle mouse to change the color box, press the right arrow at the change
mcnc
- 好不容易才从国外网站上下下来的哦，希望大家多多支持……！-eyebrows from overseas sites from the next, oh, I hope Members can support ...!
bsl_shr
- 桶形移位寄存器哦，非常好用，已经仿真验证过了，绝对没有错误-bucket shift register Oh, very convenient, has been tested by simulation, there is no wrong
CPLDxiaoche
- 智能机器小车主要完成寻迹功能，由机械结构和控制单元两个部分组成。机械结构是一个由底盘、前后辅助轮、控制板支架、传感器支架、左右驱动轮、步进电机等组成。控制单元部分主要由主要包含传感器及其调理电路、步进电机及驱动电路、控制器三个部分。本设计的核心为控制器部分，采用Altera MAX7000S系列的EPM7064LC84-15作主控芯片。CPLD芯片的设计主要在MAX+plusⅡ10.0环境下利用VHDL语言编程实现。驱动步进电机电路主要利用ULN2803作为驱动芯片。 -intelligent
adder_4bit
- 四位加法器，用OrCAD完成，可用于八位乃至十六位加法器的设计原型-four adder with OrCAD completed, can be used for eight or even 16 Adder design prototype
SCAN4
- 四位信号检测器，用OrCAD完成，用于输入信号与机内信号的监测比较-four signal detector, complete with OrCAD for the input signal and the signal for more monitoring