资源列表
sdram
- sdram控制器 这里考虑将SDRAM控制器结合目前项目开展来做相应的模块，而不做SDRAM通用控制器，这样也是考虑了FPGA的器件资源而采取的措施。同时编写的逻辑简单，没有多余的逻辑资源有利于提高控制器的速度，满足最后的设计要求。-SDRAM controller here consider SDRAM controller current projects do the corresponding module, but not so common SDRAM controller, a
baud
- vhdl 很好用于串行通信. 三个模快,发生时钟,发送和 接收过程-VHDL good for serial communication. Three die fast, occurred clock, sending and receiving process
VHDL的编程实例
- 别人的一些常用的VHDL源代码,希望对各位有用!-some others used the VHDL source code, and I hope to you and useful!
synth_fft_fpga
- 用fpga实现fft-achieve fft
PCI_144
- -- PCI Target Interface Design for XC73144 -- -- Synopsys VHDL Solution using Xilinx XC7000 Library --- PCI Target Interface Design for XC73144 -- -- Synopsys VHDL Solution using Xilinx XC7000 Library
各段程序
- 具有多种功能的电子钟：闹钟，报时和修改，定时闹钟，报时时间，带闹钟，报时开关。 -with multiple functions of electronic bell : alarm clock, timer and modification, regular alarm clock, timer, with alarm clock, timer switches.
Digital_030423
- 服务器的的板在载控制器的AHDL程序,包括原理图编译,用在EPM7128上(CPLD).-server board controller is contained in the AHDL procedures, including schematic compiler, the use EPM7128 (CPLD).
CPUverilog
- pic cpu source code. it is writed in the verilog source code. it can work on the 40Mhz high speed.
数据选择器vhd源代码
- 数据选择器，半加器，3-8译码器vhd源代码。是最近学校的实验内容。我要成会员，所以都发上来供大家参考。-data selection, half-adder ,3-8 decoder vhd source code. Recent experimental schools content. I want to become members and therefore has made onto for reference.
八位的伪随机数产生的verilog文件
- 八位的伪随机数产生的verilog文件linear-feedback-shift-register-eight pseudo-random number generator in Verilog document linear-feedback - shift-register
micro uart
- 硬件uart源程序verilog HDL，即相关文档-hardware UART Verilog HDL source, that the relevant documents
RISC8.ZIP
- 简单的一个8位RISC，Verilog HDL代码,类型为pic16c57-a simple eight RISC, Verilog HDL code, the type of pic16c57