资源列表
fifo1616
- FIFO先入先出堆栈，包括三个子程序，可根据需要选择-FIFO first in-first stack, including three subprogram, according to choose
PLI
- VCS下编译通过的PLI的实例，包括功能仿真，和可综合代码-VCS compiled under the pli example, including the functional simulation, and integrated code
自动打铃系统
- 自动打铃系统，在ＭＡＸＰＬＵＳ平台下动行，能实现计时、打铃控制等功能。 -automatic bell system, the Converter Platform animal, able to plan, a Bell controls.
edajishu
- ＥＤＡ基础教程-EDA based tutorial.
双路脉冲发生器（veralog）
- Verilog HDL 程序 双路脉冲发生器的代码 包含了键盘控制，LED显示，脉冲发生，脉冲频率测量模块 是我自己写得，希望能对你有帮助，有问题可以mail：shaojunwu1@163.com-Verilog HDL dual-channel pulse generator procedure code includes a keyboard control, LED display, pulse, pulse frequency measurement module is wr
vhdl_vga_kb
- VHDL的显示驱动程序，VHDL的PS2键盘驱动程序-VHDL display drivers, VHDL PS2 Keyboard Driver
avalon_slave_pwm
- NIOS环境PWM的USER LOGIC实例1-NIOS environment PWM USER an example LOGIC
hello_2pwm
- NIOS环境PWM的USER LOGIC实例1-NIOS environment PWM USER an example LOGIC
reg_file
- NIOS环境PWM的USER LOGIC实例3-NIOS environment PWM USER Logic Example 3
NIOS PWM HAL
- NIOS环境PWM的USER LOGIC实例4-NIOS environment PWM USER LOGIC example 4
NIOS PWM inc
- NIOS环境PWM的USER LOGIC实例5-NIOS environment PWM USER Logic Case 5
数字系统设计教程4_9
- vhdl的几个编程，4位除法器的设计和原理说明，还有8位CPU设计-VHDL programming, the four division and the design principle that there are eight CPU Design