资源列表
ADPUARTPDPRAM
- ad7606采集信号数据存入双口ram再通过串口发送出去。- ad7606 collected signal data stored in the dual port ram and then sent through the serial port.
MSK
- FPGA中实现的MSK调制，带modelsim仿真。实际系统测试通过：载波和调制波信号频率可调。调制框图请参见樊昌信 通信原理247页-MSK modulation implemented in FPGA with modelsim simulation. The actual test system: a carrier wave signal and the modulation frequency is adjustable. See Fan Changxin modulation blo
BPSK
- FPGA实现BPSK调制，带Modelsim仿真，实际系统测试通过，载波信号，调制波信号频率可调-FPGA implementation BPSK modulation with Modelsim simulation, the actual system test, the carrier signal, modulated wave signal frequency adjustable
tdc
- 线性伸展TDC的verilog，包含门级网表-TDC linear stretch of verilog, includes gate-level netlist
simple
- 一个简单的8位处理器完整设计过程及verilog代码,适合初 学ic设计的人用，并含有我个人写的指令执行过程，仅供参 考-A simple 8-bit processor and the complete design process verilog code, suitable for beginners ic design for human use, and contains my personal writing instruction execution, for ref
IMAGE_0424
- FPGA实现视频图像实时缩放功能 QUARTUS环境下测试成功-FPGA to achieve real-time video image zoom feature
Duoyewu1202
- 16路视音频光端机源代码，带开关量，RS485，E1等多业务光端机-16 Optical audio source code, with the switch, RS485, E1, etc. Optical Multiservice
biss_master_ad36_1217
- biss-c编码器读代码，测试好用，时钟要求40m -VHDL code about biss-c slave part.
2ASK
- 使用altera的FPGA实现2ASK的调制与解调，内含详细注释与完整工程-FPGA implementation using Altera modulation and demodulation of 2ASK, containing detailed notes and complete project
elevator_controller
- 采用verilog写的四层电梯控制程序，有相应的图片，报告，容易理解-Elevator controller program of four floors use the Verilog, and it includes paper and picture,and it is very easy understand.
SPDIF-interface-IP-core
- SPDIF数字音频接口的的程序，已写成通用IP核形式。-The program SPDIF digital audio interface has been written in the form of common IP core.
SPWMdaima
- spwm算法的verilog实现 对照论文表示成功-spwm algorithm verilog achieve control papers for success