资源列表
lmsFPGA
- 利用VHDL编程实现自适应滤波算法的程序，实现LMS算法-VHDL programming procedures for adaptive filtering algorithms, the LMS algorithm
PCM
- 本例设计一个码率为500kb/s，字长为8 位、帧长为128 个字、帧同步码为EB90H 的PCM 采编器。用VHDL语言实现的。-This designs a code to lead for the 500 kbs|s, the word is long for 8, the growing is synchronous code of for 128 words and for the EB90 H of PCM adopt to weave a machine.Use what VHDL
code
- 用system verilog 描述的APB总线验证源码，可以用于学习system verilog的使用。-System Verilog descr iption APB bus test source code, can be used to study the use of system Verilog
XILINX-PCI-E-DRIVER
- Xilinx公司的FPGA基于V5的开发版PCI-E驱动程序，可用作图像采集卡以及数据处理用-Xilinx s FPGA-based V5 Developer Edition PCI-E drivers can be used as a frame grabber, and data processing
LM03806
- LMK03806是一片时钟管理芯片 verilog写的 其中的寄存器设置可能不符合要求 请仔细y阅读文档 已通过仿真-LMK03806 is a clock management chip.This is writed by verilog HDL language,in which the register settings may not meet the requirements.Please read the document carefuly.
OFDM-verilog
- ofdm系统完整源代码，verilog语言编写，在ise平台测试通过-ofdm source code in verilog, run in ise fpga platform
Four-FPGA-design-techniques
- FPGA设计的四种常用思想与技巧，包括乒乓操作、串并转换、流水线操作、数据接口同步化-FPGA design of the four common ideas and techniques, including the operation of ping-pong, SERDES, pipelining, synchronization of data interface
aes_core_128bits
- 高级加密算法verilog版,包括加密和解密算法，其中有s盒，行移位，列混淆等具体算法。-aes encryption for verilog，include subbyte,shiftrow,mixcol,addroundkey.
Foundry-Flash-Verilog-code
- 几大代工厂的flash verilog源代码-flash verilog code
the-8255-LCD
- 设计一串口通信程序，波特率9600，通过RS232串口自环。自动循环发送数据串（设计在程序中）接收并存储和显示该数据串发送数据内容由键盘输入，每串数据不大于8字节。数据串单次发送由按键启动，接收端显示数据串并存储。可查询、清楚已存数据串-The design of a serial communication program, baud rate 9600, through the RS232 serial ring. Automatic cycle to send data string (d
src
- 用Verylog编写的音乐播放器代码,该文件提供了几乎完整的代码-A mp3player s code using Verylog
FM_DemodNew
- FM接收机 基于FPGA的调频收音机的设计 用VEIRLOG语言编程，利用QUARTUSii与MODELSIM联合仿真-FM receiver on FPGA FM receiver design With VEIRLOG language program, use QUARTUSii and MODELSIM joint simulation