资源列表
arithmetic_speed
- 带进位溢出为零符号位加减法arithmetic单元-verilog arithmetic cell
compmin
- 多位多个数的找最小的比较器，已仿真通过，位数个数可自行修改-Many more numbers to find the minimum comparator, through simulation, the median number of modify
crc-16b-parallel
- CRC generator in verilog hdl
38
- 采用CASE语句设计3-8译码器的示例程序-Designed using CASE statement 3-8 decoder examples of procedures
wave_gen_timing
- Clock generation in VHDL
list_ch12_08_dot_top
- VGA synchronization Code (640 x 480). It generetes VGA synchornization with only 3 bit color ang 60 hz refresh rate. The source clock is 50 MHz.
bingchuan
- 由于我是一个初学者，代码程序不是很好，希望学长多关照小弟。-Since I was a beginner, code program is not very good, I hope the seniors more than take care of the little brother.
adsawfd
- 用Verilog HDL设计3线-8线译码器，ena是译码器的使能控制端，当ena=1时译码器工作，ena=0时译码器被禁止，8个输出均为高电平 用Verilog HDL设计具有三态输出的8D锁存器。-3-to-8 line decoder, ENA is designed using Verilog HDL the decoder enable control terminal, when ena = 1 time decoder, ENA = 0 time decoder is disa
CNT10
- vhdl设计的十进制计数器，仿真测试正确，可以使用。-decimal counter vhdl design, simulation tests correctly, can be used.
gray2bin
- 格雷码转二进制 格雷码转二进制-Transfer binary Gray code binary Gray code switch
ctrl_fft
- 快速傅里叶变换的verilog 模块，经测试可用，之前用过。- U5FEB u901F u5085 u91CC u53F6 u53D8 u6362 u7684verilog u6A21 u5757 uFF0C u7ECF u6D4B u8BD5 u53EF u7528 uFF0C u4E4B u524D u7528 u8FC7 u3002
FIFO
- VHDL code for first in first out register