资源列表
SDHAnalysis
- 光纤通信中的SDH数据帧解析及提取的VHDL实现源代码，共包含帧同步、E1及F1码流提取、DCC1码流提取、帧头开销串行输出四个主要模块-SDH fiber-optic communication data frame analysis and retrieval implementation of VHDL source code, include the frame synchronization, E1 and F1 stream extraction, DCC1 stream extra
FPGA-RAM-Verilog
- 用Verilog语言编写的FPGA，对波形数据用RAM存储-Using Verilog language FPGA, using the waveform data stored in RAM
hdlc
- 基于FPGA的HDLC协议控制器，能完成插零，删除0操作。-HDLC controller base on FPGA
bubblesort1024ram
- 快速冒泡排序基于FPGA实现，有测试文件以及设计图，实现1024*32位数序的多数排序，突破传统是的REG类型少数排序，利用RAM，针对RAM中的无序数的地址调换，达到排序目的，仅供学习交流-Rapid bubble sort based on FPGA, there are test documents and design drawings to achieve 1024* 32-digit sequence of the majority of sorting, breaking trad
stopwatch
- 此程序实现计时秒表功能，时钟显示范围00.00～99.99秒，分辨度:0.01秒 采用PIC16F877单片机，6位数码管显示 开发平台：MPLAB IDE v8.30 类型：工程文件（内有C源码），已验证通过-This program achieved stopwatch function, clock display range 00.00 to 99.99 seconds Resolution: 0.01 seconds using PIC16F877 microcontro
利用LABVIEW实现板卡数据读取和发送
- 利用LABVIEW实现板卡数据读取和发送，此程序为主界面程序-labview
ad1674
- `高速AD1476 驱动程序 应用于高速AD（模数转换）与单片机接口-`AD1476 high-speed driver used in high-speed AD (analog-to-digital conversion) and single-chip interface
Spartan6
- spartan6 FPGA芯片的电路设计 Orcad原程序 公司内部文件 请下载的注意 仅供学习，不要用于商业 -the design of Spartan6 FPGA circuit. it is biult in Orcad.
duozhouqiCPU
- VHDL 多周期CPU设计。基于Quartus II平台-VHDL design of multi-cycle CPU. Quartus II-based platforms
turbo
- turbo的VHDL代码 比较好啊 易后大家多多交流啊-Comparison of the VHDL code for turbo Well you lot of the easy exchange of ah
CJQ-V1.0-fpga
- 主要实现采集电网信号的功能，源码包括控制AD7606进行AD转换，其次实现FT3数据的传输，包括转为曼彻斯特编码-Collecting grid signal to achieve the main function, including control of AD7606 source for AD conversion, followed by the realization of FT3 data transmission, including to Manchester encoding
FIFO
- 用verilog实现异步FIFO，代码中有两个模块，使用时注意顶层模块和底层模块，用quartus2即可打开直接使用。-Verilog using Asynchronous FIFO, the code has two modules, when the attention of top-level module and the bottom module, with direct access to open quartus2.