资源列表
BCD
- ROM vhdl for binary to BCD
count-for-6-data
- count data entry for 6 data and convert to 32bit floating point in verilog code.
counter
- 一個三角波產生器 適用於PWM上的使用-A triangular wave generator is suitable for PWM use
fir16.v
- 16阶FIR滤波器设计的verilog代码-Verilog 16-order FIR filter
rom
- vhdl veri log rom file
VHDLexample
- here is a VHDL example
vending_machine
- 一个简单的自动售货机控制器，投足25美分便发糖果，并且自动找零-A simple vending machine controller, 25 cents will be made every move she makes candy and give change automatically
clock_tb.v
- a verilog code for a clock.
shumadisplay
- 一种用verilog写的数码显示程序，编译通过，可下载到fpga中-program of shumadisplay,write by verilog language
simple_dual_port_ram_dual_clock
- Simple Dual-Port RAM with different read/write addresses and different read/write clock
vhdl-code-for-carwash
- automatic car wash system using verilog hdl where car moves from one state to another state for washing based on time intervel
test
- FPGA最小系统测试程序，一个LED闪烁，一个LED点亮，可以完成最小系统的验证-Minimum FPGA system test procedure, an LED flashing, an LED light, can complete the minimum system verification