资源列表
ade
- 用verilog HDL语言实现一个8位串行乘法器-An 8-bit serial multiplier with Verilog HDL language
NEW AUDIO CODEC DEVELOPMENT CODE BASE
- Hi friends, This consists of a complete system written in Verilog/TCL for VGA DISPLAY OF RESULTS INPUTTED THROUGH AUDIO CODEC AND COMPLETE SYSTEM LEVEL DESIGN ON VERILOG.
butterfly1
- FFT蝶形运算单元程序，可用于OFDM,以及任何相关数字信号处理的设计中-FFT butterfly processor program can be used in OFDM, as well as any relevant design of digital signal processing
clk_teiler
- clk for system fpga to pci card-clk for system fpga to pci card
zdsh
- 用硬件描述语言写的几个自动售货机代码，有对应测试文件，当有硬币投入时，仿真波形得到正确结果。-Hardware descr iption language code written in a few vending machines, has a corresponding test file, when a coin, the simulation waveform to get the right results.
fir1
- vhdl program for fir filter design on fpga
qww
- DAC0832 接口电路程序，这都是源程序，如果有需要用VHD的文件可联系我-DAC0832 interface circuit procedure, this is the source, if there is a need to use the VHD file can contact me
CHIAXUNG_1HZ
- divided clock from 1 Hz to 50MHz pulse output
rotary
- 采用verilog语言编写的rotary encoder程序，可以识别出旋转方向。-Rotary encoder verilog language program, you can identify the direction of rotation.
function
- How to use Function in verilog example using factorial and parity code.
alpha1_3_compensator
- 同為適用於1.8V轉1.3V必迴路 在1Mhz頻率下 RLC各為 25m 4.7u 10u 排除浮點數的int整數補償器 給有需要的同學作為參考-The same applies to 1.8V 1.3V will turn 1Mhz frequency RLC circuit at each 25m 4.7u 10u exclude floating point int integer compensation to needy students as a reference
counter_14uou
- Counter wikipediya information will help you to understand about this program-Counter wikipediya information will help you to understand about this program