资源列表
division_cordic
- verilog code for division based on cordic algorithm
BCD8
- BCD码十进制8位加法器，采用超前进位的方法-8-bit decimal BCD adder yards, using look-ahead approach
sram
- a verilog sram code. use it to manipulate sram on fpga
frediv
- EDA分频器代码vhdl例程，可用，方便理解-EDA divider vhdl code routines that can be used to facilitate the understanding of
delsig
- AD中用于调制解调的delta sigma一阶调制器-AD used for modulation and demodulation of the first order delta sigma modulator
JMUX2TO1_vhdl
- This source are usefull function in VHDL for Transfer MCU Data betwine FPGA 2 port 8bit s wide Mux -This source are usefull function in VHDL for Transfer MCU Data betwine FPGA 2 port 8bit s wide Mux
JSFP
- 奇数分频-此程序对输入频率sysclk有奇数（X）分频的功能-Odd frequency- this program has an odd number of input frequency sysclk (X) frequency function
VHDL
- 这个是基于一下的要求设计的：1、输入输出数据宽度为12位， 2、阶数为4阶段线性相位FIR滤波器， 3、类型为：低通。-This is based on what the requirements of the design: an input and output data width is 12, 2, the order of the four stages of linear phase FIR filters, 3, type: low pass
serialtoparellel
- Write a HDL Code to use as a serial to parallel converter
VHDL01
- 全加器仿真程序. 大家可以参考下 ，本人检查无误。无毒。如有问题，请来信咨询。-Full adder simulation program. You can refer to, I check the accuracy. Non-toxic. If you have any questions, please contact us advice.
decoder35
- decoder verilog. it is a 3 t0 5 decoder that compile with modelsim.
BBooth
- 基verilog 布斯乘法器 4位位宽，本人不才，仅做参考-Booth multiplier based verilog