资源列表
EDA3
- 该程序是一个带记数使能，异步复位，带进位输出的增一 二十进制记数器，记数结果由共阴极七段数码管显示-The program is a band count enable, asynchronous reset, into digital output by 12 decimal counter, counting the results from the common cathode seven-segment LED display
fir_srg
- FIR algorithm VHDL FPGA
Ram-block-code
- It is a VHDL code for Block RAM
fenlu
- 适合在光纤中传输，对数字信号进行解复用，具体是2:8分路器-Suitable for optical fiber transmission of digital signal solution reuse, and the concrete is 2:8 optical device
uart_rx
- receiver module of uart protocol in verilog hdl
60code
- 本源代码基于VHDL语言，实现了模60的异步复位同步计数功能。-VHDL source code is based on the language, to achieve the synchronization module 60 of the asynchronous reset counter function.
VHDL_counter_source_code
- VHDL Counter Source Code
aa
- 这个程序就是序列检测器的vhdl实现，真麻烦啊-This program is the sequence detector vhdl achieve real trouble
key_piano
- 基于FPGA的Verilog语言开发的电子琴测试程序，很好哦-Verilog FPGA-based language developed organ testing procedures, very well
CLOCK
- 有關時鐘的兩個程式，一個是好改的時鐘，一個是可重新計時的Counter-frequency eliminator and counter
edge_detector_logic
- verilog code for edge detection logic
max197
- verilog编写的状态机控制A/D芯片MAX197正常工作-use verilog write the state machine which is used to meke the A/D chip working!