资源列表
register_test
- This a vhdl code for tseting the colour gen code for fpga-This is a vhdl code for tseting the colour gen code for fpga
ADC
- CPLD ADC采集控制源码CPLD ADC采集控制源码-CPLD ADC
m_xulie
- 在quaritusII的开发环境下，verilog语言编写的m序列发生器代码，这种算法简短而有效，非常实用。-In quaritusII development environment, verilog language of m sequence generator code, this algorithm brief but effective, very practical.
serial_to_para
- verilog状态机实现并串转换serial_to_para,本人已调试并仿真成功，绝对可用-verilog state machine and string conversion，i think it is very important to someone who is ready to learn verilog
BUFG_CLK0_SUBM
- xilinx DCM 应用程序，完全可用-xilinx DCM applications, fully available
cnt_up_down
- It s a counter which count to up, when on the all positions are "1", it count to down
hdb3
- 这是一个很全的HDB3译码的verilog程序，用于FPGA入门所用，verilog的入门很好的程序-This is a very wide of the HDB3 decoding verilog program for entry-FPGA used, verilog entry procedures for good
RW_flash_con
- FLASH-RW,完成FLASH的读写操作 FLASH-RW,完成FLASH的读写操作-FLASH-RW,完成FLASH的读写操作
no1_arrengment_if
- no1_arrengment_if by vhdl using xlinx
clock
- 时钟发生器，利用系统时钟获得需要的时钟信号-Clock generator, using the system clock to obtain the required clock signals
csa1
- carry save adder block1
VEND
- 此为第14.7.8章的门级描述代码 实现的的自动售报机 文件名为vend.gv，注意与vend.v区分-gate level descr iption Section 14.7.8 of a FSM for a newspaper vending machine