资源列表
vhdl_codes
- D-flip flop vhdl implement code
AD
- 有限状态机的设计——0809 A/D转换实验-VHDL for ADC0809
LED
- 流水灯设计原则以及源代码的编写,主要在器件上实现CPLD-Flowing water light design principle and the writing of the source code, mainly for the CPLD device
TCD1001P-driver-Verilog
- 东芝线阵CCD-TCD1001P驱动程序源代码，verilog编写-Toshiba linear CCD-TCD1001P driver source code, Verilog write
compare
- 用verilog实现文件输入的比较器，如果同一时间输入的数据相同则输出高电平，否则输出低电平，达到比对的效果。-Use verilog implementation file input comparator, if the input data at the same time the same output high level, otherwise the output low level, to achieve the effect of alignment.
UART
- Universal async Transmitter Receiver
fast_16bit_counter
- 16位快速计数器,速度达到180MHz,16位快速计数器,速度达到180MHz-16bit counter
IO_controll
- this a controller, mainly for the nexys2 board based around the spartan 3E fpga from xilinx. controlls various outputs and inputs.-this is a controller, mainly for the nexys2 board based around the spartan 3E fpga from xilinx. controlls various outpu
TVR2
- A Modern Stream Cipher - Trivium
er
- 秒表 东北大学秦皇岛分校 电子设计自动化 实验-Stopwatch Northeastern University at Qinhuangdao electronic design automation experiment
dingshijishu.vhd
- 基于VHDL语言环境的定时计数程序，可进行简单的定时计数，供大家改进开发。-Simple timer count timer count program based on the VHDL language environment for improved development.
latch
- 频率计设计的一个模块，即锁存器，实现了对六位计数结果和溢出信号over的锁存功能 -Frequency meter design a module latch, the six count results and overflow signal over the latch function