资源列表
2
- 利用VHDL语言编程，产生一组PWM波，PWM波的频率为10kHz,占空比00—100 可调-VHDL programming, resulting in a set of PWM wave PWM wave frequency is 10kHz, and 00-100 duty cycle adjustable
AsgPart4
- verilog prormmaing language exercises, introduction-verilog prormmaing language exercises, introduction
clkdiv
- 《深入浅出玩转FPGA学习课程特权同学——实验代码》时钟分频-The students easily understood how to play the FPGA courses privilege- experimental code clock frequency division
Ring0
- température FPGA projet fichier te mpérature FPGA projet fichier te mpérature FPGA projet fichier-température FPGA projet fichier température FPGA projet fichier température FPGA projet fichier température FPGA projet fichier température FPGA projet
LED
- VHDL超声波测距代码，大家看看吧，测试过能用,实体名我改成了LED-VHDL ultrasonic ranging code, you have a look, tested can be used, the entity name I changed it to LED
DOT_LED
- 点亮LED，适用于FPGA 初学者，很不错的例子，简单、易懂-dot led
carlight
- 汽车后尾灯的控制代码，经过xilinx公司的fpga演示通过。
vga
- VGA显示控制：时序控制+像素点的颜色处理显示十字光标（vorilog）-VGA Display Control: Timing Control+ pixel color processing and display cross cursor (vorilog)
AD_filter
- AD递推平均滤波算法，采用verilog完成，可直接使用。-AD recursive average filter algorithm, using verilog complete, can be used directly.
leading_8
- This program gives a count of leading zeros in 16 bit number.
shunmaguanxianshidianlu
- 用VHDL语言编写一个八位数码管显示电路，每个数码管的八个段分别连在一起，八个数码管分别由八个选通信号选择。被选通的数码管显示数据，其余关闭-With the VHDL language to write a eight digital tube display circuit, each digital tube eight segments are connected together, the eight digital tube are respectively composed of
ram_sp_ar_sw.v
- this is a verilog source code for Single Port RAM Synchronous Read/Write.