资源列表
DAC
- 实现AD模数转换的作用，已通过验证，功能可以实现-Analog to digital converter to achieve the role of AD, has been validated, the function can be achieved
SHIFT_REG
- FPGA verilog 移位寄存器的源代码-FPGA verilog This is a shift reg module.
Lab10_Part1
- Verilog code for Altera Part1 Lab10
shipin
- vhdl编程 视频传输格式时序 可应用于液晶显示
gcd_lcm
- 求两个100以内整数的最大公约数和最小公倍数，只用加法和减法运算-Find the greatest common divisor of two integers less than 100 and the least common multiple, only addition and subtraction
CRC
- 对26比特的帧结构进行6比特的CRC处理，输出26+6=32的帧结构。VHDL代码实现-26 bits of the frame structure of 6-bit CRC processing, output 26+6 = 32 frame structure. VHDL code
GCD1
- GCD算法的FSMD实现。即利用有限状态机和数据路径-GCD algorithm order which FSMD using finite state machine and data path
daconfig
- 一般DA模数转换器的VHDL配置程序，输入为14位串口输出，状态机实现的。-General AD ADC VHDL configuration program, the output is 14 serial output, the state machine implementation.
txd5
- 异步发送电路是基于MAXPLUS2软件开发的一种实用电路,已经编译成功,可使用.-asynchronous circuit is based on the development of software MAXPLUS2 a practical circuit, has been successfully compiled, can be used.
conv3
- Program to implement convolution through VHDL-Program to implement convolution through VHDL...
Scrambler
- Scrambler most widly used an data transfer operation in PCI.
rite
- GUSS算法里面的读模块的程序，非常的有价值的哦，合适开发组的利用，可以修改成别的模块功能-The procedures of the the GUSS algorithm inside of the read module, very valuable, the use of appropriate development group can be modified into other module functions.