资源列表
p_s2m_onechnl
- 这是一个并转串的代码示例，将并行的数据转换为串行数据-This is one and transferred to the string code example, the parallel data is converted into serial data
Verilog-Accumulator
- the folder contains two files written by Verilog HDL. the first one is an implementation of an accumulator that takes serial data as an input, and its output will be an accumulated sum of each consecutive four input samples. the second file is a te
dds-design
- * DEscr iptION: DDS design BY PLD DEVICES. * * AUTHOR: Sun Yu * * HISTORY: 12/06/2002 *-* DEscr iptION : DDS BY PLD design Online. * * AUTHOR : Sun Yu * * HISTORY : 12/06/2002 *
12_convert
- convert.vhd 本例是从程序包中提取出来的，不能单独编译-convert.vhd the cases from the package is extracted, not separate compiler
Params
- SDRAM控制器Verilog员代码，设计参数模块，整个模块的所有参数定义-SDRAM controller member Verilog code, design parameter module, the entire module of all parameters defined
xuanlvbo
- 数字图像处理中有许多种滤波方法，本方法是一种特殊的方法，即旋律波，有比较明显的效果-xianlvbo
show1234
- ：在四个七段LED数码管上显示数字“1234”-: In the four seven-segment LED digital display the number " 1234"
my_fir
- Verilog 写的FIR滤波器，modelsim仿真通过-Verilog write FIR filter, modelsim simulation through
suanfa
- 通过移位和类型转换 将FPGA的DA输出和AD输入转换为对应LCD12864在屏幕上对应的点-Shift and type conversion through the FPGA DA output and AD input is converted to the corresponding LCD12864 corresponding point on the screen
pid
- It is a verilog code for a vedic multiplier using a barrel shifter
Led_dec
- LED decoder code in verilog for Spartan 3 FPGA
NL_prsg9
- vhdl的伪随机序列发射器程序，已经过仿真，仿真正确且能够成功应用