资源列表
AND_gate
- VHDL AND gate source code
sine.txt
- THIS IS CODE FOR VHDL
Input_filter
- Module for filtering input digital signal
vhdl_fir
- 1、输入输出数据宽度为12位， 2、阶数为4阶段线性相位FIR滤波器， 3、类型为：低通。 -1, input and output data width is 12, 2, 4 stages of the order of linear phase FIR filter, 3, type: low pass.
Buffer8x32
- Para controlar el flujo del algoritmo SHA
decoder_using_with
- decoder_using_with verilog code
Karasimsek
- A VHDL implementation of Karasimsek
Adder4bit
- VHDL full adder 4 bit
contador_n_bits
- n-bits counter vhdl with testbench. contador de nbits en vhdl con simulacion.
flowbyte_shifter
- Module that can shift stream by one or more bits. It can be use for sinhronization in STM.
codelock
- VHDL语言编写的数字密码锁，异步清零，带有开锁，关锁，修改密码的功能-VHDL language digital code lock, asynchronous clear, with a lock, lock, change the password function
f_de_ck564
- 根据数据校准时钟，实现频率时钟校准，能够使数据准确输入进入ram-clk jiaozhun shixian shujuzhunqueduru