资源列表
Double_Pulse_Test
- 利用VHDL语言描述出一个双脉冲，可任意设置两脉冲长和中间时间间隔。(A double pulse is described in VHDL language, and the two pulse length and the intermediate time interval can be arbitrarily set.)
sdram_test
- 自己实现的一个基于SOPC架构的SDRAM模块-Own implementation of an architecture based on SOPC SDRAM module
FIR---ALEX
- Filter c language, better validation, able to run the filter C language-FIR filter VHDL, you can use, though a bit......
ex8_232
- 这是一个用于自收自发的uart通讯代码，包括波特率设置模块、uart收发模块，上位机使用串口调试助手(Uart module is used to communite with PC in the way of spontaneous collection, including buad setting and transceiver. Upper computer is serial debugging assistant.)
CPU
- 基于32位MIPS流水线CPU，由自己独立完成，-Pipelined 32-bit MIPS-based CPU, by themselves independently,
sos_module
- 用FPGA实现sos摩尔密码，即输出电平信号短长短。就是有次序的控制输出莫斯密码的“点”，“画”和“间隔”。而 control_module.v 是一个简单的定时触发器，每一段时间都会使能sos_module.v。-Realized by FPGA sos mole password, the output signal level of short duration. There is a sequence of output control points Moss password,
sd_card
- 基于FPGA的SD控制器,ALTERA的3C25开发板上可跑-SD controller base on FPGA，implement in altera NEEK board.
数字预失真
- 采用VHDL编写的数字预失真模块，主要用于提高功放效率
demo_LCDdisplay
- DE2-70 LCDdisplay验证 FPGA-DE2-70 LCDdisplay authentication
UVM_TEST
- UVM 的 入门实例，一个完整的能够跑通的实例。其中包括DUT代码，Testbench代码，还有搭建过程说明。很适合用来学习UVM入门。-This paper describes an approach to using Accellera s UVM, the Universal Verification Methodology, for functional verification by mainstream users. The goal is
eightbitadd
- 用VHDL语言实现8位的并行加法器，不同于行波进位加法器-8-bit parallel adder with VHDL, unlike the ripple carry adder
Verilog_coding_style
- verilog 编码规范，共包含3个PDF文档，供学习参考。-verilog coding style, include 3 seperate pdf files, just for studying or refrence.