资源列表
zhuanpan.rar
- 增量式光电编码器输出四分频脉冲计数，分别为A，B两路信号,Incremental optical encoder pulse count output frequency of a quarter, namely A, B two-way signal
Sequencedetector
- 用VHDL语言实现的序列检测器 （以1010111为例）-Sequence detector (for example 1010111)
Multiplier
- 4 bit multiplier written in behavioral VHDL, using logic gate logic. inputs are A and B (4 bit each) and output is C (8 bits).
vhdlcodes4
- VHDL coding for 4X1 mux in behavioural modelling and for 16X1 mux in structural modelling.
pam
- pam verilog 简单的一个pam verilog实现代码，仅有调制无解调-pam verilog pam verilog implementation of a simple code, not only modulation demodulation
configue_vga
- RDA1005L数字信号衰减芯片SDI接口配置代码-RDA1005L chip digital signal attenuation SDI interface configuration code
vga
- vga设计,实现横/竖/混合图象,混合编排,直接使用.-The design of vga,to acchive imags of differents arrages.
counter7
- 4bit counter in verilog
code
- 通过对十字路口交通灯控制系统的设计，掌握不同进制计数归零的描述方法以 及通过信号使进程进行相互通信的方法。-Through the intersection traffic light control system design, master describes different methods to zero and the decimal counting processes via signal to communicate with each method.
ps2_vga_top
- PS2 WITH VGA FOR VERILOG ALTERA DE2
ASK_DEMODULATION_AND_TEST_CODE
- ASK解调VHDL程序及仿真,项目已使用，好用-ASK demodulation VHDL procedures and simulation, the project has been used, easy to use
code-hmwk7
- Make the required flag signals using the input clock signal (clk) and input flag (TKN). Whenever the TKN signal is activated, a sequence of activation of flag signals should be performed based on the timing diagram