资源列表
VHDL_code
- 基于FPGA的AD,DA,LCD,LED,CAN,I2C,PS2,VGA以及一些通讯ASK,FSK等的VHDL源程序，所有程序已通过调试，需要的拿走。-FPGA-based AD, DA, LCD, LED, CAN, I2C, PS2, VGA, and some communications ASK, FSK, etc. VHDL source code, all procedures have been debugging, need to take.
mig007
- XILINX memory interface generator. XILINX的外部存储器接口。-XILINX memory interface generator.
fftshixian
- 基于FPGA编写的verilog代码，在xilinx上仿真实现FFT变换-FPGA-based verilog code written in xilinx FFT transform Simulation
EPM240
- 开发板配套教程里的很多个实验 方便从初学开始 含有VHDL和verilog HDL语言-Development board supporting the many tutorial easy experiments start from the beginner with the language VHDL and verilog HDL
CORDIC_SINE
- xilinx的ISE工程，用CORDIC算法做DDS生成正弦波-xilinx the ISE project to do with the CORDIC algorithm generates sine DDS
radio_na_TEA5767
- It contains the source code files use the module on the radio TEA5767 I2C written in AVR Studio 4 for Atmega8. It also includes circuit diagram and documentation.
ucos_niosii
- 在FPGA硬件体系下，搭建软核处理器NIOSII，进而用NIOSII运行ucos操作系统，从硬件到软件完全实现用户定制-In the FPGA hardware system, the structures of soft-core processor NIOSII, and then run with NIOSII ucos operating system, from hardware to software to fully implement custom
FPGA_DDS
- 基于FPGA的DDS信号发生器产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-FPGA-based VHDL source DDS signal generator and the test stimulus file matlab model simulation in modelsim adopted under
MD5Transform
- 本人设计的一个基于FPGA平台用verilogHDL设计的MD5加密，供FPGA学习者学习参考-a MD5 encoder designed by me.It s a learning code for FPGA learner
EP2C8Q_Nios_TFT_LCD
- EP2C8Q，利用nios驱动2.4寸TFT屏-EP2C8Q，use nios to let 2.4_tft screen work normal
FPGA_project
- 基于FPGA目标版上采集码盘数据，并将其发送至上位机-Based on the FPGA target version of the collecting the code disk data and send it first bit machine
BCH_VLSI
- 使用HLS完成BCH编码的运算通路的设计，纯组合逻辑，对于65nm工艺可跑上1GHz。已经组合逻辑分为了多个部分，可在每一个部分之间插流水线。 附上可综合的纯RTL Code以及C++代码，以及Modelsim仿真。 可通过我的优化选项来学习如何优化HLS工具生产的代码。(BCH Encoder realized using HLS tool. Combinational logic.)