资源列表
VHDL
- 再FPGA上經由VGA顯示一半黑一半白的圖示-By the FPGA and then VGA display half black half white icon
multi8
- 8位乘法器-multi8
speed_test
- QuartusII运行环境下的计数器的VHDL源代码，其中有部分文档说明。-QuartusII operating environment under the counter VHDL source code, some of them documented.
carLightsMealy
- carlights example with mealy based vhdl good for study
2s_Compl_2_4.0.vhd
- complement calculator
GAME
- 经典数学游戏 实现人猫狗鼠过河的经典游戏的状态机的编程-classic mathematic game
sp
- vhdl code to change bits stream from serial to parallel
sequence_dectect
- sequence_dect 实现6个状态，即6种选择的状态机。状态机的一个极度确切的描述是它是一个有向图形，由一组节点和一组相应的转移函数组成。-sequence_dectect to six states, namely, six options the state machine. State machine of an extremely precise descr iption is that it is a directed graph, by a group of nodes and
decoder
- decoder code in verilog/vhdl language
main
- led灯控制，可以看到其灯灭和灯亮的现象-control, you can see its lights out and lights phenomenon led lights
mult_piped_8x8_2sC_h1
- 這是由我自己寫的8位元乘法器,雖然不是最好的但是希望能提供同學們課業上的好幫助-It was written by my own 8 yuan multiplier, though not the best but hope to provide better help students on academic
mod.verilog
- 计算两个数值间的最大公约数和最小公倍数。-calculate two numbers greatest common divisor and lowest common multiple.