资源列表
openmsp430_latest.tar
- The openMSP430 is a 16-bit microcontroller core compatible with TI s MSP430 family (note that the extended version of the architecture, the MSP430X, isn t supported by this IP). It is based on a Von Neumann architecture, with a single address s
crc_check
- 实现CRC冗余校验 ，可以对8bit的数据进行crc32进行校验(Implementing CRC redundancy check)
Connected Component Analysis-Labeling
- 别人写的物体连通域计算的verilog 源代码(Object connected domain calculation of the Verilog source code)
VHDLdeep
- 详细的讲述了VHDL的精髓，使您更加深入的了解到VHDL的应用-VHDL的详细介绍和深入了解
de1_t1
- DE1的LED流水灯，数码管显示，可修改参数完成自定义的显示，有UART串口通信代码，VGA信号显示图片。-DE1 of the LED water lamp, LED display, you can modify the parameters to complete a custom show that UART serial communication code, VGA signal display pictures.
vivado 从此开始配套资料
- vivado入门使用介绍，初学者入门学习(vivado Instructional pdf)
rt_32bit
- 通过Verilog实现的基于FPGA实现429总线格式转换接收程序-FPGA code for receive 429 message
10658624
- 超星新上架新书，PDF格式 书名(超星SS号)：CPLD系统技术入门与应用_10658624-Superstar' s New Book, PDF format title (Superstar SS No.): CPLD entry system technology and application _10658624
CommunicationICdesign
- 通信IC设计的附件里面是通信IC设计这本书各章节的源代码非常详细有利于fpga通信开发-Communication IC design of the annex which is the communication IC design The chapters of the book are very detailed in the source code is conducive to fpga communication development
SOPC-book
- 一本关于设计SOPC的书，讲的很详细，看后很有收获。-SOPC a book on the design, speaking in great detail, looking after the great harvest.
project_fir_test
- 基于verilog的FIR滤波器设计，使用BASYS３作为开发工具-Verilog based FIR filter design, the use of BASYS3 as a development tool
mt9d112_ddr2
- 镁光MT9基于FPGA图像采集模块，该模块可同时采集两路视频信号。其包括完整的时序和接口、ddr2内存数据写入和存储、qsys系统的搭建、FPGA与NIOS II联合设计-Micron MT9 based on FPGA image acquisition module, the module can simultaneously capture two video signals. Including the complete timing and interface, ddr2 memory