资源列表
DDS_sine
- DDS扫频信号源的FPGA实现，有的是verilog编写，欢迎下载-Sweep frequency signal source of DDS FPGA realizing, have a plenty of verilog write, welcome to download
FreCore8051
- 基于ACTEL FPGA的测频模块,测频精度非常高！-ACTEL FPGA-based module of the frequency measurement, frequency measurement accuracy is very high!
class_fifo
- FPGA内部fifo的调用,使用Verilog对其进行编程-The FPGA internal fifo calls, use Verilog programming on it
pipeline_cpu
- 流水线cpu，pipeline_cpu,南大计算机系计算机组成原理实验-Pipeline cpu, pipeline_cpu, Nanjing University Department of Computer Science Computer Composition principle experiment
mips789_latest.tar
- mips789..32bit implementation ...found it on the internet..cyclone EPIC target device
Alliance-VLSI-CAD-System-master
- Alliance VLSI CAD Design System and Soutce code....include a all RTL2GDSII Flowchart
edge
- 关于nios ii处理器上led试验的测试程序以及方法-something about led
EDA-ppt
- 电子设计自动化EDA课件，介绍了vhdl语言，并附有设计实例-Electronic design automation (EDA) courseware, vhdl language, with design examples
FPGA_CCD
- 基于FPGA的CCD扫描缺陷检测实时数据处理技术的研究-FPGA-based real-time data of the CCD scan defect detection processing technology
ug898-vivado-embedded-design
- Vivado Design Suite User Guide 是学习Vivado 入门文档，源自xilinx，权威易懂-Vivado Design Suite User Guide 是学习Vivado 入门文档，源自xilinx，权威易懂，
0124406513
- Synthesis using VHDL
VHD-L-QUARTUS--Counter
- 基于QUARTUS软件的VHDL语言开发，文件中含有VHDL语言设计的分频器，加法减法计数器，并生成有原理图，只要有QUARTUS软件即可仿真运行。-VHDL QUARTUS Counter