资源列表
vga_gui
- VGA 的 ip core 编写程序时需要逐点编写-VGA-ip core programming point by point to write
calendar
- 拥有预约时间提醒，阴阳历转换，调整时间等功能。-With appointment reminders, lunisolar calendar conversion, adjusting the time and other functions.
sdram_ov5640_vga
- 基于ov5640摄像头的实时视频采集，运用FPGA开发板(Complete the real-time image acquisition and VGA display function, the camera for the ov5640 series)
DE1-SoC_User_manual
- DE1-soc使用说明书，详细的介绍了DE1的硬件配置，使用方式-DE1-soc manual, a detailed descr iption of the hardware configuration DE1 of use
vga
- vga code for vhdl to show image on moniter
VIRTUAL INPUT OUTPUT VERILOG CODE
- THE IS CODE THAT USED THE VERILOG WHERE VIO FUNCTION USED
MAX121_test
- max121，ad采集芯片，spi接口，fpga测试逻辑，verilog语言-max121, ad capture chip, spi interfaces, fpga test logic, verilog language
CMOS-Circuit-Design-Layout-and-Simulations-Baker-
- a guide for simulation , synthesis ebook
PS
- 基于DE2平台的PS2键盘可视化虚拟钢琴的设计实现-Implemented based on the DE2 platform PS2 keyboard virtual piano design visualization
FUNDAMENTALSOFDIGITALLOGICWITHVERILOGDESIGN
- FUNDAMENTALS OF DIGITAL LOGIC WITH VERILOG DESIGN 将verilog和数电很好的结合在一起讲解
FPGA_exp2
- 调节数码管显示的文件，适用于CYCLONE II 开发板， 用VHDL语言编写，非常适合移植进数字钟中以实现调节时间的功能。 多模块设计简单明了。-Adjust digital display files for CYCLONE II development board, using VHDL language, it is very suitable for transplantation into digital clock to realize the function of regula
SP_SCH(Executable)
- 调度器一般包括SP、RR、WFQ等，SP调度指的是绝对高优先级调度，此种调度不带权重概念，按照优先级进行调度。四个按键作为端口有效指示，2个LED发光二极管指示此时调度的端口号，可以按下KEY3按键，按下按键代表当前按键输入无效，然后观测LED，没有按下的时候LED1 LED0都发光，按下KEY3按键的时候LED1发光 LED0不发光，代表此时调度端口为2，不按下时候代表调度端口为3。 -The scheduler typically include SP, RR, WFQ, etc., SP