资源列表
BasicRSA
- VHDL RSA cypher for FPGA
VGA
- 用Verilog HDL编写的VGA显示程序，可实现图像的显示，在DE2-70上测试通过，有很大的参考价值。-Prepared using Verilog HDL VGA display program, image display DE2-70 test by great reference value.
fft-IPcore
- verilog编写，基于ISEfft的ip核研究，数据生成采用matlab，有仿真截图-verilog written, ip nuclear research ISEfft based on data generated using matlab, there are simulation screenshot
四通道DDS信号发生器
- 四通道DDS信号发生器，很好用的代码，大家一起分享(Four-channel DDS signal generator)
xapp780
- FPGA Security Mechanism. VHDL Source
dtsmg
- 动态数码管的实时显示和应用，主要是实现一个简单的没有控制位的时分秒的数字钟；六位数码管的前两位实现小时；三四位显示分钟；最后两位显示秒。主要有四个模块。-Real-time display and application of dynamic digital tube, primarily to implement a simple no control bits when every minute digital clock six digital realization of the fi
adc
- 使用verilog 硬件描述语言编写的ad采样模块，希望对大家有用。(Using Verilog hardware descr iption language written in AD sampling module, I hope useful for everyone)
5_ADC_Lab
- 基于altera公司MAX10型FPGA的ADC调试程序-ADC-based debugger altera company MAX 10 type of FPGA
Code-Verilog
- this code verilog-this is code verilog
sin
- 用VHDL语言编写实现以下功能：用PLL，复位器，分频器，同步时钟，计数器来产生正弦波，再在其上加扰，用FIR滤波器进行滤波整形，最后得到输出。-Using VHDL language to achieve the following functions: PLL, reset, clock synchronization, frequency divider, counter to generate sine wave, and then scrambling on the filter sh
VGA-code
- 基于verilog 的vga设计，有多种分辨率可供选择-the design of vga driven based on Verilog。it s a variety of resolutions to choose
SOPC123456
- SOPC软件编程基础，用实例讲解，非常适合初学者。