资源列表
bw_scoresource
- This the bowling score source code. Edit tool is xilinx corp ISE. I used the Modelsim for simulation.-This is the bowling score source code. Edit tool is xilinx corp ISE. I used the Modelsim for simulation.
Multiprocessor
- Multiprocessor using NIOS2 and Quartus 10.1sp1
FPGA-Development-Raiders-Innovative
- FPGA开发全攻略— 工程师创新设计宝典 上册 基础篇 2009年2月 1.0版-FPGA Development Raiders- Innovative Design Engineers Book Collection on the basis of articles in February 2009 Version 1.0
FPGAcaptures-1
- fpga全攻略，介绍了FPGA的开发和应用，适用于各个层次的工程师学习-fpga all captures, describes the development and application of FPGA for engineers at all levels of learning
Development-QuanGongLve1
- FPGA 开发全攻略（上） 学习FPGA的好资料-FPGA development QuanGongLve ， the good learning FPGA information
FPGA_devlelop_in_embed-
- fpga开发全攻略基于嵌入式系统的系列丛书 -fpga-based embedded systems development Raiders of the series
sp605PCIe
- xilinx评估板sp605的PCIe的verilog源程序(已经经过调试)-Evaluation Kit for PCIe-sp605 xilinx verilog source (which has been commissioning)
cycloneIVGX_4cgx150_fpga
- Altera公司的Cyclone 4 GX系列的原理图和pcb文件，注意，是capture及pdf格式的原理图和allegro格式的PCB文件，稍微修改修改就可以用在您的设计中，让fpga的硬件设计变得简单和高效。-Altera Corporation' s Cyclone 4 the GX series of schematic and pcb files, note that the capture and pdf format schematic and allegro PCB fo
RS9600
- 这是用FPGA实现的RS232通信接口程序，波特率为9600，由于RS232的波特率是有容差的，因此该对时序做了专门的优化，以确保接收到正确的数据，（因为用FPGA做接口和协议是大材小用了，而且比较麻烦）-This is achieved using FPGA RS232 communication interface program, 9600, due to the RS232 baud rate is tolerance, so the timing made specifically o
LG_Z37LZ5D_LCD_TV_Service_Manual
- lg lcd service dokuments
quartus
- 流水灯状态机的一段式描述和二段式描述还有三段式描述的Verilog源码-Light water section of the state machine and the two-stage type descr iption descr iption descr iption of Verilog source code as well as three-
pwm-generators
- 此程序的功能是基于xilinx公司ISE平台实现pwm发生器。-Function of this program is to achieve pwm generator based company ISE xilinx platform.