资源列表
Xilinx_verilog
- 这是Xilinx公司公布的对于大学生的FPGA教程，由浅入深，非常适合初学者-This is Xilinx company released for FPGA tutorial college students, it is very suitable for beginners
UART_E6
- 用于测试FPGA串口接收，带singelTap。便于观测。(Used to test the FPGA serial port reception, with singelTap. Convenient observation.)
lv_fpga_chipscope
- 在labview fpga中借助Chipscope调试代码-ChipScope Debugging with LabVIEW FPGA CLIP
VERILOG
- 一本很好的Verilog课件，通俗易懂简单明了适合初学者，给大家分享了~-A very good Verilog courseware, simple easy to understand for beginners, for everyone to share ~
veriog_hdl
- 华中科技大学硬件描述语言教学文档，包含硬件描述语言所有知识要点-Huazhong University of hardware descr iption language teaching document that contains all the knowledge points hardware descr iption language
Verilog
- 一个我觉得很不错的课件，讲了Verilog的语言基本要点，和集成电路的一些基础知识-I think a very good courseware, speaking of the basic elements of Verilog language, and some basic knowledge of integrated circuits
A4_Uart_Top
- 提供一般FPGA开发板的Uart通讯协议(Provides the Uart communication protocol for the general FPGA development board)
Verilog-hdl-resources
- verilogr的相关教程，比较完整的讲述的verilog 设计的相关知识点-verilog related text resources
fft_512
- 采用Xilinx提供的VHDL FFT ip核实现512点FFT，可以实现使能控制、时钟控制等功能-Using Xilinx provides VHDL FFT ip core to achieve implementation of 512 points FFT, with enable control, clock control and other functions
Stopwatch
- 在quatus平台，verilog语言编写的秒表代码。实现功能开始，暂停，复位，显示暂停。在Cyclone2上运行通过。-In quatus platform, verilog language stopwatch code. Achieve functional start, pause, reset, pause the display. On Cyclone2 run through.
MultiCLKCPU
- 本设计实现了多周期CPU的设计，运行环境是quatrus2；该多周期CPU可以处理22条32位指令（具体指令见源码，绝不坑人）。压缩包内含有源代码，程序模块表和实验报告以及详细的设计图，是学习verilog的好材料啊。-The Design and Implementation of a multi-cycle CPU design, operating environment is quatrus2 the multi-cycle CPU can handle 22 32 instructi
CPU
- 一个多周期CPU的完整设计，quartus平台，Verilog实现，内含实验报告，和详细的各模块功能表-Complete a multi-cycle CPU design, quartus platform, Verilog implementation, includes lab reports, and a detailed menu of each module