资源列表
CPU
- 4位和8位，8运算，QUARTUS简易处理器,能在Quartus上运行-4 and 8-bit, 8 operations, QUARTUS simple processors, can run on the Quartus
uart_fifo
- FPGA与PC的串口通信代码，使用了FIFO作为数据的缓存。-FPGA and PC serial communication code, use the FIFO as cached data.
ping_pong2LED
- 用QuartusII13.0软件，DE1开发板，支持VGA的显示屏实现的乒乓球游戏，同时可实现七段数码管计分，球碰撞声等功能-With QuartusII13.0 software, DE1 development board that supports VGA screen realization of table tennis game, while achieving seven-segment LED scoring, ball impact sound, and other funct
yuyin_jiami
- 基于quarusII仿真软件，进行模块化设计，设计达到的目的是对进来的语音信号进行加密处理-Based on quarusII simulation software, modular design, designed to meet the incoming voice signal is encrypted
NIOSII_TFT
- 基于FPGA的NIOSII_TFT做的做的正弦波很连贯的显示在液晶屏上面，FPGA主要做信号的产生，而NIOSII主要是驱动液晶画活出波形！-FPGA-based NIOSII_TFT do make a very coherent sine wave displayed on the LCD screen above, FPGA mainly to do signal generation, while NIOSII mainly driven liquid crystal painting
ELIPTIC
- Matlab Security Eliptic curve crypto Matlab Security Eliptic curve crypto Matlab Security Eliptic curve crypto Matlab Security Eliptic curve crypto Matlab Security Eliptic curve crypto Matlab Security Eliptic curve crypto Matlab Security Eliptic curv
DE2
- 辛辛苦苦的作品应用于DE2 的 开发。。希望对大家有用。-hard work for Dictyophora development. . We hope that the right useful.
NCO
- 利用Quartus中的IP核进行NCO的设计源文件-IP cores in Quartus NCO design source files
《Verilog HDL设计与实战》配套代码(1)
- 《Verilog HDL设计与实战》配套代码 verilog源程序(Verilog HDL design and actual combat code Verilog source program)
CORDIC_ATAN
- FPGA实现反正切功能，工程原件，包括测试文件，能够很好实现该功能(FPGA implements arctangent function, original engineering)
soc_ip-2016-10-12
- 基于ISE14.7，软核SOC的自定义IP核源码，8个寄存器，全部引出，可以作为FL-FS通讯接口，附带几个其他驱动IP核-Based on the ISE14.7, soft-core SOC custom IP core source code, 8 registers, all derived, can be used as FL-FS communication interface, with several other drivers IP core
DDS
- 内含DDSFPGA程序和51单片机控制程序和报告一份-Containing DDSFPGA procedures and 51 procedures and reporting a single-chip control